MATRA MHS
L 67205
8K × 9 / 3.3 Volts CMOS Parallel FIFO
Introduction
The L67205 implements a first-in first-out algorithm, Using an array of eigh transistors (8 T) memory cell and
featuring asynchronous read/write operations. The FULL fabricated with the state of the art 1.0 µm lithography
and EMPTY flags prevent data overflow and underflow. named SCMOS, the L 67205 combine an extremely low
The Expansion logic allows unlimited expansion in word standby supply current (typ = 1.0 µA) with a fast access
size and depth with no timing penalties. Twin address time at 55 ns over the full temperature range. All versions
pointers automatically generate internal read and write offer battery backup data retention capability with a
addresses, and no external address information are typical power consumption at less than 5 µW.
required for the MHS FIFOs. Address pointers are
For military/space applications that demand superior
automatically incremented with the write pin and read
levels of performance and reliability the L 67205 is
pin. The 9 bits wide data are used in data communications
processed according to the methods of the latest revision
applications where a parity bit for error checking is
of the MIL STD 883 (class B or S) and/or ESA SCC 9000.
necessary. The Retransmit pin reset the Read pointer to
zero without affecting the write pointer. This is very
useful for retransmitting data when an error is detected in
the system.
Features
D First-in first-out dual port memory
D Single supply 3.3 ± 0.3 volts
D 8192 × 9 organisation
D Fast access time
D Fully expandable by word width or depth
D Asynchronous read/write operations
D Empty, full and half flags in single device mode
D Retransmit capability
55, 60, 65 ns, commercial, industrial military
and automotive
D Bi-directional applications
D Battery back-up operation 2 V data retention
D High performance SCMOS technology
D Wide temperature range :
– 55 °C to + 125 °C
D 67205L low power
67205V very low power
Rev. C (10/11/94)
1