Datasheet > AL1I-67204V-55

AL1I-67204V-55

更新时间： 2024-01-28 02:56:20

品牌	Logo	应用领域
TEMIC		先进先出芯片
页数	文件大小	规格书
16页	145K
描述
FIFO, 4KX9, 55ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28

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技术参数
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AL1I-67204V-55 技术参数

生命周期：	Obsolete	零件包装代码：	DIP
包装说明：	DIP,	针数：	28
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	风险等级：	5.84
最长访问时间：	55 ns	周期时间：	70 ns
JESD-30 代码：	R-GDIP-T28	长度：	37.25 mm
内存密度：	36864 bit	内存宽度：	9
功能数量：	1	端子数量：	28
字数：	4096 words	字数代码：	4000
工作模式：	ASYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-40 °C	组织：	4KX9
可输出：	NO	封装主体材料：	CERAMIC, GLASS-SEALED
封装代码：	DIP	封装形状：	RECTANGULAR
封装形式：	IN-LINE	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	5.72 mm
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	NO
技术：	CMOS	温度等级：	AUTOMOTIVE
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	宽度：	15.24 mm
Base Number Matches：	1

AL1I-67204V-55 数据手册

MATRA MHS

L 67203/L 67204

single word to be read after one word has been written to In the write flow-through mode (figure 18), the FIFO

an empty FIFO stack. The data is enabled on the bus at stack allows a single word of data to be written

(tWEF + tA) ns after the leading edge of W which is immediately after a single word of data has been read

known as the first write edge and remains on the bus until from a full FIFO stack. The R line causes the FF to be

the R line is raised from low to high, after which the bus reset, but the W line, being low, causes it to be set again

will go into a three-state mode after tRHZ ns. The EF line in anticipation of a new data word. The new word is

will show a pulse indicating temporary reset and then will loaded into the FIFO stack on the leading edge of W. The

be set. In the interval in which R is low, more words may W line must be toggled when FF is not set in order to write

be written to the FIFO stack (the subsequent writes after new data into the FIFO stack and to increment the write

the first write edge will reset the Empty Flag) ; however, pointer.

the same word (written on the first write edge) presented

to the output bus as the read pointer will not be

incremented if R is low. On toggling R, the remaining

words written to the FIFO will appear on the output bus

in accordance with the read cycle timings.

Figure 4. Block Diagram of 1536 × 9 / 3072 × 9 FIFO Memory (Depth expansion).

67203/204

FULL

EMPTY

67203/204

Figure 5. Compound FIFO Expansion.

– Q

(N–8)

– Q

(N–8)

L 67203/204

R . W . RS

DEPTH

EXPANSION

BLOCK

DEPTH

EXPANSION

BLOCK

DEPTH

EXPANSION

BLOCK

– I

(N–8)

– I

I – I

(N–8) N

Notes : 6. For depth expansion block see section on Depth Expansion and Figure 4.

7. For Flag detection see section on Width Expansion and Figure 3.

Rev. C (10/11/94)

1...4 5 678 9 10...16

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与AL1I-67204V-55相关器件

型号	品牌	描述	获取价格	数据表
AL1I-67204V-60	TEMIC	FIFO, 4KX9, 60ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67204V-65	ATMEL	FIFO, 4KX9, 65ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67205L-55	TEMIC	FIFO, 8KX9, 55ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67205L-60	TEMIC	FIFO, 8KX9, 60ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67205L-65	TEMIC	FIFO, 8KX9, 65ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格
AL1I-67205V-55	TEMIC	FIFO, 8KX9, 55ns, Asynchronous, CMOS, CDIP28, 0.600 INCH, CERAMIC, DIP-28	获取价格

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