Datasheet > AK8451

AK8451

更新时间： 2022-06-03 03:10:23

品牌	Logo	应用领域
AKM		/
页数	文件大小	规格书
42页	705K
描述
1 channel-input 16 bit 6MSPS ADC

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中文翻译

获取价格

数据手册

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AK8451 数据手册

ASAHI KASEI

[AK8451]

AFE block, Analog characteristics

(AVDD=3.3V, DRVDD=3.3V, MCLK=40MHz,Single Edge Mode, Ta=25°C,

unless otherwise specified)

Item

VCOM voltage

VRP voltage

VRN voltage

Min.

Typ.

Reference voltage

Max.

Unit

Remarks

1.4

1.9

0.9

1.5

2.0

1.0

1.6

2.1

1.1

VREF voltage

1.0

1.1

1.2

+0.1

Band Gap error

@ I=10mA ( diff. @I=0mA)

@ I=-10mA( diff. @I=0mA)

at current sink error

at current source error

-0.1

Analog input

1.98

Maximum signal input level

Absolute gain

V_p-p

MSPS

kΩ

–0.7

–1.50

0.7

At DC mode (Note 1)

At CDS mode (Note 1)

–0.60

0.30

Sampling rate

Input reference level

VCLP input resistence

Input signal range

Clamp level (VCLP voltage)

Clamp resister

1.1

1.5

At DC mode

At DC mode （Note 2）

At CDS mode

1.98

AVDD

2.18

2.08

kΩ

CDS advantage

-40

(note 11)

Black level correction DAC

Resolution

Correctable range

Internal offset voltage

bit

(Note 3)

(Note 4)

(Note 5)

±215

±240

±265

–50

PGA(Programmable Gain Amp.) circuit

Resolution

Min. gain

Max. gain

13.9

bit

13.3

14.5

(Note 7)

Video ADC

Resolution

DNL

INL

bit

LSB

–16

-96

+16

+96

±32

Noise

Output noise

LSB_rmsPGA min.

LSB_rmsPGA max.

Power Consumption

Analog part

31.5.

35.5

0.1

At DC mode (Note 7)

power dissipations

At CDS mode (Note 7)

At power down (Note 8)

(Note 9)

Digital output driver power

dissipation

(Note 1) 0dB is defined at the gain where ADC output reaches its full-scale when 1.98Vpp signal

is input with PGA setting at 00h.

(Note 2) At 2 bit bus mode.

(Note ３) CISIN0 input signal must be in this range which is referenced to AVSS.

(Note 4) Monotonicity guaranteed.

(Note 5) ±50 mV of the total correctable range is used for internal offset adjustment.

MS0937-E-01

2011/04

1...5 6 789 10 11...42

中文翻译

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