Datasheet > AK8772

AK8772

更新时间： 2024-01-09 08:12:45

品牌	Logo	应用领域
AKM		/
页数	文件大小	规格书
5页	150K
描述
AK8772 is ultra-small Hall effect IC of a single silicon chip composed of Hall element and a signal processing IC

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技术参数
数据手册

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AK8772 技术参数

生命周期：	Contact Manufacturer	Reach Compliance Code：	unknown
风险等级：	5.77	主体宽度：	1.1 mm
主体高度：	0.37 mm	主体长度或直径：	1.4 mm
滞后：	3.6 mT	最大磁场范围：	4.2 mT
最小磁场范围：	-4.2 mT	安装特点：	SURFACE MOUNT
最大工作电流：	0.15 mA	最高工作温度：	85 °C
最低工作温度：	-30 °C	最大输出电流：	0.5 mA
输出范围：	0.40-1.45V	输出类型：	DIGITAL VOLTAGE
封装形状/形式：	RECTANGULAR	传感器/换能器类型：	MAGNETIC FIELD SENSOR,HALL EFFECT
最大供电电压：	5.5 V	最小供电电压：	1.6 V
表面贴装：	YES	端接类型：	SOLDER
Base Number Matches：	1

AK8772 数据手册

Monolithic Hall Effect ICsꢀAK-series

Shipped in packet-tape reel(5000pcs/Reel)

AK8772 is ultra-small Hall effect IC of a single silicon chip composed of Hall element and a signal processing IC.

AK8772

Bipolar Hall

Supply Voltage

Power down

Function

Ultra High

Sensitivity

Bop：1.8mT

Output

CMOS

SON

Effect Latch

1.6～5.5Ｖ

Notice:It is requested to read and accept "IMPORTANT NOTICE" written on the back of the front cover of this catalogue.

●Features

・Precision Bipolar Hall Effect Latch

・Power manageability through "PDN" pin

ꢀCurrent consumption in Power down mode is less than 1μA

・Low current consumption at active mode : less than avg.

ꢀ150μA@VDD=3V

・Ultra small SON package : 1.1×1.4×t0.37mm, Halogen free

●Operational Characteristics

Vout

VoH

S or N

Package top

Package bottom

VOL

N or S

Brp

Bop

Magnetic flux density

●Functional Block Diagram

1：VDD

Item

OSC

Function

Generates operating clock

3：PDN

Switch

Timing logic Generates timing signal requires for Chopper SW, AMP

and COMP

4：OUT

2：VSS

Hall Element Hall element fabricated by CMOS process

Chopper SW Performs chopping in order to cancel the offset voltage

ꢀ

of Hall sensor

AMP

Reduce offset voltage and amplifies Hall output voltage

OSC

Timing Logic

Hall

Element SW

Chopper

Schmitt

Trigger

Latch

Logic

Output

Stage

AMP

Schmitt Trigger Hysteresis comparator

Latch

Output Stage CMOS output, During the power down mode, output

is latched in its previous state

12 3 4 5

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