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AK591024ASW-80 PDF预览

AK591024ASW-80

更新时间: 2024-11-10 03:55:47
品牌 Logo 应用领域
ACCUTEK 动态存储器
页数 文件大小 规格书
2页 93K
描述
DRAM

AK591024ASW-80 数据手册

 浏览型号AK591024ASW-80的Datasheet PDF文件第2页 
Accutek  
Microcircuit  
Corporation  
AK591024AS / AK591024AG  
1,048,576 Word X 9 bit, CMOS  
Dynamic Random Access Memory  
DESCRIPTION  
Front View  
30-Pin SIM  
The Accutek AK591024 high density memory modules is a random  
access memory organized in 1 Meg x 9 bit words. The assembly  
consists of two 1 Meg x 4 and one 1 Meg x 1 DRAMs in surface  
mount packages mounted on the front side of a printed circuit board.  
The module can be configured as a leadless 30 pad SIM or a leaded  
30 pin SIP. This packaging approach provides a better than 6 to 1  
density increase over standard DIP packaging.  
+
+
30  
1
30-Pin SIP  
The operation of the AK591024 is identical to two 1 Meg x 4 plus one  
1 Meg x 1 DRAMs. For the lower eight bits, the data input is tied to  
data output and brought out separately for each 1 Meg x 4 device,  
with common RAS, CAS and WE control. The OE pins are tied to  
Vss which dictates the use of early-write cycles to prevent conten-  
tion of D and Q. Since the Write-Enable (WE) signal must always go  
low before CAS in a write cycle, Read-Write and Read-Modify-Write  
operation is not possible. For the ninth bit, the data input (D9) and  
data output (Q9) pins are brought out separately and controlled by a  
separate PCAS for that bit. Bit nine is generally used for parity.  
+
+
1
FEATURES  
· Power:  
· 1,048,576 x 9 bit organization  
1.650 Watt Max Active (60 nS)  
1.485 Watt Max Active (70 nS)  
1.265 Watt Max Active (80 nS)  
23.5 mWatt Standby (max)  
· Optional 30 Pad SIM (Single In-Line Module) or 30 Pin leaded  
SIP (Single In-Line Package)  
· JEDEC standard pinout  
· Operating free air temperature: 0o to 70oC  
· Upward compatible with and AK594096 and AK5916384  
· Downward compaitble with AK59256  
· Common CAS, RAS and WE control for the lower eight bits  
· 1024 refresh cycles/16ms  
· Separate PCAS control for D9 and Q9  
· Functionally and Pin compatible with AK491024  
PIN NOMENCLATURE  
PIN ASSIGNMENT  
FUNCTIONAL DIAGRAM  
PIN #  
1
SYMBOL  
Vcc  
CAS  
DQ1  
A0  
PIN #  
SYMBOL  
DQ5  
A8  
DQ1 - DQ8  
D9  
Data In / Data Out  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
A0 - A9  
+
A0 - A9  
RAS  
CAS  
WE  
10  
Data In  
2
RAS  
CAS  
WE  
+
+
+
*
*
*
3
A9  
Q9  
Data Out  
DQ1 +  
DQ1  
DQ2  
DQ3  
DQ4  
*
4
NC  
DQ2  
DQ3  
DQ4  
+
+
+
A0 - A9  
CAS, PCAS  
RAS  
Address Inputs  
Column Address Strobe  
Row Address Strobe  
Write Enable  
5v Supply  
*
*
*
5
A1  
DQ6  
WE  
OE  
OE  
Q
*
6
DQ2  
A2  
7
Vss  
DQ7  
NC  
8
A3  
A0 - A9  
RAS  
CAS  
WE  
DQ1  
DQ2  
DQ3  
DQ4  
WE  
*
*
*
9
Vss  
DQ3  
A4  
Vcc  
10  
11  
12  
13  
14  
15  
DQ8  
Q9  
DQ5 +  
*
DQ6  
DQ7  
DQ8  
+
+
+
*
*
*
Vss  
Ground  
A5  
RAS  
PCAS  
D9  
*
NC  
No Connect  
DQ4  
A6  
A0 - A9  
RAS  
CAS  
MODULE OPTIONS  
A7  
Vcc  
*
*
PCAS  
+
* WE  
Leadless SIM: AK591024ASP  
Leaded SIP: AK591024AGP  
D9  
Q9  
+
+
D
*
*

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