Datasheet > AGLN010V5-UCG36I

AGLN010V5-UCG36I

更新时间： 2024-10-31 20:08:23

品牌	Logo	应用领域
美高森美 - MICROSEMI		栅可编程逻辑
页数	文件大小	规格书
150页	7693K
描述
Field Programmable Gate Array, 260 CLBs, 10000 Gates, CMOS, PBGA36, 3 X 3 MM, 0.80 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, UCSP-36

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技术参数
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AGLN010V5-UCG36I 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	VFBGA,	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.61
JESD-30 代码：	S-PBGA-B36	长度：	3 mm
可配置逻辑块数量：	260	等效关口数量：	10000
端子数量：	36	最高工作温度：	85 °C
最低工作温度：	-40 °C	组织：	260 CLBS, 10000 GATES
封装主体材料：	PLASTIC/EPOXY	封装代码：	VFBGA
封装形状：	SQUARE	封装形式：	GRID ARRAY, VERY THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	NOT SPECIFIED	可编程逻辑类型：	FIELD PROGRAMMABLE GATE ARRAY
认证状态：	Not Qualified	座面最大高度：	0.8 mm
最大供电电压：	1.575 V	最小供电电压：	1.425 V
标称供电电压：	1.5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	BALL	端子节距：	0.4 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	3 mm	Base Number Matches：	1

AGLN010V5-UCG36I 数据手册

Revision 17

IGLOO nano Low Power Flash FPGAs

with Flash*Freeze Technology

High-Performance Routing Hierarchy

Features and Benefits

•

Segmented, Hierarchical Routing and Clock Structure

Low Power

Advanced I/Os

•

nanoPower Consumption—Industry’s Lowest Power

1.2 V to 1.5 V Core Voltage Support for Low Power

Supports Single-Voltage System Operation

•

1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages—up to 4 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V

Low Power Active FPGA Operation

Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

Easy Entry to / Exit from Ultra-Low Power Flash*Freeze Mode

•

Wide Range Power Supply Voltage Support per JESD8-B,

Allowing I/Os to Operate from 2.7 V to 3.6 V

Wide Range Power Supply Voltage Support per JESD8-12,

Allowing I/Os to Operate from 1.14 V to 1.575 V

I/O Registers on Input, Output, and Enable Paths

Selectable Schmitt Trigger Inputs

•

Small Footprint Packages

•

As Small as 3x3 mm in Size

Wide Range of Features

Hot-Swappable and Cold-Sparing I/Os

Programmable Output Slew Rate and Drive Strength

Weak Pull-Up/-Down

•

10,000 to 250,000 System Gates

Up to 36 kbits of True Dual-Port SRAM

Up to 71 User I/Os

IEEE 1149.1 (JTAG) Boundary Scan Test

Pin-Compatible Packages across the IGLOO Family

Reprogrammable Flash Technology

Clock Conditioning Circuit (CCC) and PLL^†

•

130-nm, 7-Layer Metal, Flash-Based CMOS Process

Instant On Level 0 Support

Up to Six CCC Blocks, One with an Integrated PLL

Configurable Phase Shift, Multiply/Divide, Delay

Capabilities, and External Feedback

Single-Chip Solution

Retains Programmed Design When Powered Off

250 MHz (1.5 V systems) and 160 MHz (1.2 V systems) System

Performance

•

Wide Input Frequency Range (1.5 MHz up to 250 MHz)

Embedded Memory

In-System Programming (ISP) and Security

•

1 kbit of FlashROM User Nonvolatile Memory

SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

•

ISP Using On-Chip 128-Bit Advanced Encryption Standard

(AES) Decryption via JTAG (IEEE 1532–compliant)

†

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

True Dual-Port SRAM (except × 18 organization)

†

•

FlashLock Designed to Secure FPGA Contents

1.2 V Programming

Enhanced Commercial Temperature Range

•

Tj = -20°C to +85°C

AGLN010 AGLN015¹AGLN020

AGLN060

AGLN125

AGLN250

IGLOO nano Devices

IGLOO nano-Z Devices

System Gates

AGLN030Z¹AGLN060Z¹AGLN125Z¹AGLN250Z¹

10,000

15,000

20,000

30,000

60,000

512

1,536

125,000

250,000

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

260

128

384

172

520

256

768

1,024

3,072

2,048

6,144

Flash*Freeze Mode (typical, µW)

RAM Kbits (1,024 bits)

–

4,608-Bit Blocks

–

FlashROM Kbits (1,024 bits)

Secure (AES) ISP

–

Yes

2,3

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os (packaged device)

Maximum User I/Os (Known Good Die)

–

Package Pins

UC/CS

UC36

QN48

UC81,

CS81

QN68

UC81, CS81

QN48, QN68

VQ100

CS81

QFN

VQFP

QN68

VQ100

Notes:

1. Not recommended for new designs.

2. AGLN030 and smaller devices do not support this feature.

3. AGLN060, AGLN125, and AGLN250 in the CS81 package do not support PLLs.

4. For higher densities and support of additional features, refer to the IGLOO and IGLOOe datasheets.

† AGLN030 and smaller devices do not support this feature.

June 2013

12 3 4 5 6 7...150

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与AGLN010V5-UCG36I相关器件

型号	品牌	获取价格	描述	数据表
AGLN010V5-UCG36Y	MICROSEMI	获取价格	Field Programmable Gate Array, 260 CLBs, 10000 Gates, 250MHz, 260-Cell, CMOS, PBGA36, 3 X
AGLN010V5-UCG36YI	MICROSEMI	获取价格	FPGA
AGLN010V5-UCG81	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN010V5-UCG81ES	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN010V5-UCG81I	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN010V5-UCG81PP	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN010V5-UCG81Y	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN010V5-UCG81YES	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN010V5-UCG81YI	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology
AGLN010V5-UCG81YPP	MICROSEMI	获取价格	IGLOO nano Low Power Flash FPGAs with Flash*Freeze Technology

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