Datasheet > AGL015V5-CSG144I

AGL015V5-CSG144I

更新时间： 2024-10-29 06:36:39

品牌	Logo	应用领域
ACTEL		/
页数	文件大小	规格书
212页	6544K
描述
IGLOO Low-Power Flash FPGAs with Flash Freeze Technology

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中文翻译

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数据手册

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AGL015V5-CSG144I 数据手册

v1.3

IGLOO Low-Power Flash FPGAs

with Flash*Freeze Technology

Advanced I/O

Features and Benefits

• 700 Mbps DDR, LVDS-Capable I/Os (AGL250 and above)

Low Power

• 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 4 Banks per Chip

• 1.2 V to 1.5 V Core Voltage Support for Low Power

• Supports Single-Voltage System Operation

• 5 µW Power Consumption in Flash*Freeze Mode

• Low-Power Active FPGA Operation

• Flash*Freeze Technology Enables Ultra-Low Power

Consumption while Maintaining FPGA Content

• Easy Entry to / Exit from Ultra-Low-Power Flash*Freeze

Mode

• Single-Ended

I/O

Standards:

LVTTL,

LVCMOS

3.3 V / 2.5 V / 1.8 V / 1.5 V / 1.2 V, 3.3 V PCI / 3.3 V PCI-X , and

LVCMOS 2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and M-

LVDS (AGL250 and above)

• I/O Registers on Input, Output, and Enable Paths

‡

• Hot-Swappable and Cold-Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

High Capacity

• Weak Pull-Up/-Down

• 15 k to 1 Million System Gates

• Up to 144 kbits of True Dual-Port SRAM

• Up to 300 User I/Os

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the IGLOO Family

Clock Conditioning Circuit (CCC) and PLL¹

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal, Flash-Based CMOS Process

• Live-at-Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Six CCC Blocks, One with an Integrated PLL

• Configurable

Phase

Shift, Multiply/Divide,

Delay

Capabilities, and External Feedback

• Retains Programmed Design When Powered Off

• Wide Input Frequency Range (1.5 MHz up to 250 MHz)

In-System Programming (ISP) and Security

Embedded Memory

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

• 1 kbit of FlashROM User Nonvolatile Memory

Standard (AES) Decryption (except ARM -enabled IGLOO

• SRAMs and FIFOs with Variable-Aspect-Ratio 4,608-Bit RAM

devices) via JTAG (IEEE 1532–compliant)

Blocks (×1, ×2, ×4, ×9, and ×18 organizations)

H^•igh^Fla-P^she^Lr^of^co^krmance Routing Hierarchy

to Secure FPGA Contents

A^•RM^TruP^er^Do^uc^ae^l-s^Ps^oo^rtr^SS^RAu^Mpp^(eo^xr^ct^epi^tn^×I¹G⁸⁾LOO FPGAs

• M1 IGLOO Devices—Cortex™-M1 Soft Processor Available

with or without Debug

• Segmented, Hierarchical Routing and Clock Structure

IGLOO Product Family

IGLOO Devices

AGL015

AGL030

AGL060 AGL125

AGL250

AGL400

AGL600

AGL1000

ARM-Enabled IGLOO Devices

System Gates

M1AGL250 M1AGL400 M1AGL600 M1AGL1000

15 k

128

384

30 k

256

768

60 k

512

1,536

125 k

1,024

3,072

250 k

2,048

6,144

400 k

–

600 k

–

1 M

–

Typical Equivalent Macrocells

VersaTiles (D-flip-flops)

Flash*Freeze Mode (typical, µW)

RAM kbits (1,024 bits)

4,608-Bit Blocks

9,216

13,824

24,576

–

108

144

–

FlashROM Bits

1 k

–

1 k

–

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

1 k

Yes

Secure (AES) ISP

Integrated PLL in CCCs

–

VersaNet Globals

I/O Banks

Maximum User I/Os

133

143

194

235

300

Package Pins

UC/CS

4,5

UC81/CS81

CS121

CS196

CS281

QFN

QN68

QN48, QN68, QN132

QN132

QN132 QN132

VQFP

FBGA

VQ100

FG144

VQ100

FG144

FG144,

FG256,

FG484

FG144,

FG256,

FG484

FG144,

FG256,

FG484

Notes:

1. AES is not available for ARM-enabled IGLOO devices.

2. AGL060 in CS121 does not support the PLL.

3. Six chip (main) and twelve quadrant global networks are available for AGL060 and above.

4. The M1AGL250 device does not support this package.

5. Device/package support TBD

6. For higher densities and support of additional features, refer to the IGLOOe Low-Power Flash FPGAs with Flash*Freeze

Technology handbook.

1 AGL015 and AGL030 devices do not support this feature.

‡ Supported only by AGL015 and AGL030 devices.

December 2008

12 3 4 5 6 7...212

中文翻译

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与AGL015V5-CSG144I相关器件

型号	品牌	获取价格	描述	数据表
AGL015V5-CSG144PP	ACTEL	获取价格	IGLOO Low-Power Flash FPGAs with Flash Freeze Technology
AGL015V5-CSG144PP	MICROSEMI	获取价格	IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
AGL015V5-CSG144Y	MICROSEMI	获取价格	IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
AGL015V5-CSG144YES	MICROSEMI	获取价格	IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
AGL015V5-CSG144YI	MICROSEMI	获取价格	IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
AGL015V5-CSG144YPP	MICROSEMI	获取价格	IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
AGL015V5-CSG484ES	MICROSEMI	获取价格	IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
AGL015V5-CSG484I	MICROSEMI	获取价格	IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
AGL015V5-CSG484PP	MICROSEMI	获取价格	IGLOO Low Power Flash FPGAs with Flash*Freeze Technology
AGL015V5-CSG484YES	MICROSEMI	获取价格	IGLOO Low Power Flash FPGAs with Flash*Freeze Technology

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