Datasheet > AFS600-FG256GI

AFS600-FG256GI

更新时间： 2024-11-13 03:59:51

品牌	Logo	应用领域
美高森美 - MICROSEMI		栅
页数	文件大小	规格书
14页	139K
描述
Field Programmable Gate Array,

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AFS600-FG256GI 数据手册

Product Brief

Fusion Family of Mixe_®d-Signal Flash FPGAs

With Optional Soft ARM Support

–

Frequency Range: Input (1.5–350 MHz), Output (0.75–

350 MHz)

Features and Benefits

High Performance Reprogrammable

Flash Technology

Low Power Consumption

•

Single 3.3 V Power Supply with On-Chip 1.5 V Regulator

Sleep and Standby Low Power Modes

•

Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process

Nonvolatile, Retains Program When Powered-Off

Live at Power-Up (LAPU) Single-Chip Solution

350 MHz System Performance

In-System Programming (ISP) and Security

•

Secure ISP with 128-Bit AES Via JTAG

FlashLock to Secure FPGA Contents

Embedded Flash Memory

Advanced Digital I/O

•

User Flash Memory 2 Mbit to 8 Mbit in Density

•

1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

Bank-Selectable I/O Voltages – Up to 5 Banks per Chip

Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V / 2.5 V /

1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X and LVCMOS 2.5 V / 5.0 V

Input

–

Configurable 8-, 16-, or 32-Bit Data Path

Runtime Read and Write During with 10 ns Access Read-

Ahead Mode

•

1 kbit of Additional FlashROM

Integrated A/D Converter (ADC) and Analog I/O

•

Differential I/O Standards: LVPECL and LVDS

–

Hot-Swappable I/Os

Programmable Output Slew Rate, Drive Strength, and Weak

Pull-Up/Down

•

Up to 600 ksps in 8-, 10-, and 12-Bit Resolution Modes with

Internal 2.56 V or External Reference Voltage

ADC: Up to 30 Scalable Analog Input Channels

High Voltage Direct-Connect Input Tolerance 12 V

Current Monitor and Temperature Monitor

Built-In I/O Registers

700 Mbps DDR Operation

•

Up to 10 MOSFET Gate Driver Outputs

•

Pin-Compatible Packages Across the Fusion Family

–

Interfaces to P- or N-Channel Power MOSFETs with

Programmable 1, 3, 10, 30 µA and 25 mA Drive Strengths

SRAMs and FIFOs

•

Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (x1, x2, x4, x9,

and x18 organizations available)

On-Chip Clocking Support

•

External 32 kHz to 20 MHz Crystals Oscillator or Internal

100 MHz RC Oscillator (accurate to 1%)

•

True Dual-Port SRAM (except x18)

Programmable Embedded FIFO Control Logic

•

Programmable Real-Time Counter (RTC)

6 Clock Conditioning Circuits (CCCs) with 1 or 2 integrated PLLs

Soft ARM7™ Core Support in M7 Fusion Devices

•

CoreMP7S and CoreMP7Sd (with debug)

–

Phase Shift, Multiply/Divide, and Delay Capabilities

Table 1 • Fusion Family

Fusion Devices

AFS090

AFS250

AFS600

AFS1500

ARM7-Ready Fusion Devices

System Gates

M7AFS600

M7AFS1500

90,000

2,304

250,000

6,144

600,000

13,824

7,500

5,237

Yes

1,500,000

38,400

32,000

29,878

Yes

Tiles (D-Flip-Flops)

Usable Tiles with CoreMP7S

General

Information

Usable Tiles with CoreMP7Sd

Secure (AES) ISP

PLLs

Yes

Globals

Flash Memory Blocks (2 Mbits)

Flash Memory Bits

2 M

1 k

2 M

1 k

4 M

1 k

8 M

1 k

Memory

FlashROM Bits

Usable RAM Blocks (4,608 bits)

Usable RAM kbits

252

Analog Quads

Analog Input Channels

Gate Driver Outputs

I/O Banks (+ JTAG)

Analog and I/Os

Maximum Digital I/Os

114

172

278

Analog I/Os

Notes:

1. Refer to the CoreMP7 datasheet for more information.

2. Some debug tools require 10 digital I/Os for external connection.

February 2006

12 3 4 5 6 7...14

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与AFS600-FG256GI相关器件

型号	品牌	获取价格	描述	数据表
AFS600-FG256I	ACTEL	获取价格	Actel Fusion Mixed-Signal FPGAs
AFS600-FG256I	MICROSEMI	获取价格	Fusion Family of Mixed Signal FPGAs
AFS600-FG256K	MICROSEMI	获取价格	Field Programmable Gate Array, 600000 Gates, CMOS, PBGA256, 1 MM PITCH, FBGA-256
AFS600-FG256PP	MICROSEMI	获取价格	Fusion Family of Mixed Signal FPGAs
AFS600-FG256PP	ACTEL	获取价格	Actel Fusion Mixed-Signal FPGAs
AFS600-FG256Y	MICROSEMI	获取价格	Fusion Family of Mixed Signal FPGAs
AFS600-FG256YES	MICROSEMI	获取价格	Fusion Family of Mixed Signal FPGAs
AFS600-FG256YI	MICROSEMI	获取价格	Fusion Family of Mixed Signal FPGAs
AFS600-FG256YK	MICROSEMI	获取价格	FPGA
AFS600-FG256YPP	MICROSEMI	获取价格	Fusion Family of Mixed Signal FPGAs

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