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AFS600-2FG484K PDF预览

AFS600-2FG484K

更新时间： 2024-11-12 03:29:31
品牌 Logo 应用领域
美高森美 - MICROSEMI 时钟栅可编程逻辑
页数 文件大小 规格书
294页 16776K
描述
FPGA

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中文翻译

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AFS600-2FG484K 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：BGA, BGA484,22X22,40Reach Compliance Code：unknown
风险等级：5.9最大时钟频率：350 MHz
JESD-30 代码：S-PBGA-B484JESD-609代码：e0
湿度敏感等级：3输入次数：172
逻辑单元数量：13824输出次数：172
端子数量：484封装主体材料：PLASTIC/EPOXY
封装代码：BGA封装等效代码：BGA484,22X22,40
封装形状：SQUARE封装形式：GRID ARRAY
峰值回流温度（摄氏度）：225电源：1.5,3.3 V
可编程逻辑类型：FIELD PROGRAMMABLE GATE ARRAY认证状态：Not Qualified
子类别：Field Programmable Gate Arrays表面贴装：YES
技术：CMOS端子面层：TIN LEAD
端子形式：BALL端子节距：1 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20

AFS600-2FG484K 数据手册

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Revision 2  
Extended Temperature Fusion Family of Mixed Signal FPGAs  
•
6 Clock Conditioning Circuits (CCCs) with 2 Integrated PLLs  
Features and Benefits  
–
–
Phase Shift, Multiply/Divide, and Delay Capabilities  
Frequency: Input 1.5–350 MHz, Output 0.75–350 MHz  
Extended Temperature Tested  
•
Each Device Tested from –55°C to 100°C Junction Temperature  
Low Power Consumption  
•
•
High-Performance Reprogrammable Flash Technology  
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator  
Sleep and Standby Low-Power Modes  
•
•
•
•
Advanced 130-nm, 7-Layer Metal, Flash-Based CMOS Process  
Nonvolatile, Retains Program when Powered Off  
Instant On Single-Chip Solution  
In-System Programming (ISP) and Security  
•
•
ISP with 128-Bit AES via JTAG  
350 MHz System Performance  
FlashLock® Designed to Secure FPGA Contents  
Embedded Flash Memory  
Advanced Digital I/O  
•
User Flash Memory – 4 Mbits to 8 Mbits  
•
•
•
1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation  
Bank-Selectable I/O Voltages – Up to 5 Banks per Chip  
Single-Ended I/O Standards: LVTTL, LVCMOS  
3.3 V / 2.5 V /1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and  
LVCMOS 2.5 V / 5.0 V Input  
–
–
Configurable 16- or 32-Bit Datapath  
10 ns Access in Read-Ahead Mode  
•
1 Kbit of Additional FlashROM  
Integrated A/D Converter (ADC) and Analog I/O  
•
•
•
•
•
•
Up to 12-Bit Resolution and Up to 600 Ksps  
Internal 2.56 V or External Reference Voltage  
ADC: 30 Scalable Analog Input Channels  
High-Voltage Input Tolerance: –10.5 V to +12 V  
Current Monitor† and Temperature Monitor Blocks  
Up to 10 MOSFET Gate Driver Outputs  
•
Differential I/O Standards: LVPECL, LVDS, B-LVDS, M-LVDS  
–
–
Built-In I/O Registers  
700 Mbps DDR Operation  
•
•
Hot-Swappable I/Os  
Programmable Output Slew Rate, Drive Strength, and Weak  
Pull-Up/Pull-Down Resistor  
•
Pin-Compatible Packages across the Fusion® Family  
–
–
P- and N-Channel Power MOSFET Support  
Programmable 1, 3, 10, 30 µA, and 20 mA Drive Strengths  
SRAMs and FIFOs  
•
•
ADC Accuracy Is Better than 1%  
Variable-Aspect-Ratio 4,608-Bit SRAM Blocks (×1, ×2, ×4, ×9, and  
×18 organizations available)  
On-Chip Clocking Support  
•
•
•
Internal 100 MHz RC Oscillator (Accurate to 1%)  
Crystal Oscillator Support (32 KHz to 20 MHz)  
Programmable Real-Time Counter (RTC)  
•
•
True Dual-Port SRAM (except ×18)  
Programmable Embedded FIFO Control Logic  
Soft ARM® Cortex™- M1 Fusion Devices (M1)  
•
ARM Cortex-M1–Enabled  
Table 1 • Fusion Extended Temperature Devices  
Fusion Devices  
AFS600  
AFS1500  
*
ARM Cortex-M1 Devices  
M1AFS600  
M1AFS1500  
System Gates  
600,000  
13,824  
Yes  
2
1,500,000  
38,400  
Yes  
2
Tiles (D-flip-flops)  
General Information  
Secure (AES) ISP  
PLLs  
Globals  
18  
18  
Flash Memory Blocks (2 Mbits)  
Total Flash Memory Bits  
FlashROM Bits  
2
4
4M  
1,024  
24  
8M  
Memory  
1,024  
60  
RAM Blocks (4,608 bits)  
RAM kbits  
108  
10  
270  
10  
Analog Quads  
Analog Input Channels  
Gate Driver Outputs  
I/O Banks (+ JTAG)  
Maximum Digital I/Os  
Analog I/Os  
30  
30  
10  
10  
Analog and I/Os  
5
5
172  
40  
223  
40  
Note: *Refer to the Cortex-M1 product brief for more information.  
† Refer to Table 2 on page IV for details.  
January 2013  
I
© 2013 Microsemi Corporation  
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