Data Sheet
ADuM7704
SPECIFICATIONS
VDD1 = 4.5 V to 20 V, V DD2 = 3 V to 5.5 V, VIN+ = −50 mV to +50 mV, VIN− = 0 V, TA = −40°C to +125°C (1±-lead SOIC_W), TA = −40°C to
+105°C (8-lead SOIC_IC), MCLKIN frequency (fMCLKIN) = 20 MHz, tested with a sinc3 filter, and a 25± decimation rate, unless otherwise
noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
STATIC PERFORMANCE
Resolution
16
Bits
Filter output truncated to 16 bits
Integral Nonlinearity (INL)1
Differential Nonlinearity (DNL)1
Offset Error1
2
8
0.99
0.13
0.18
0.25
0.6
LSB
LSB
mV
mV
µV/°C
µV/°C
µV/V
% FSR
ppm/°C
µV/°C
ppm/V
Guaranteed no missed codes to 16 bits
Initial at TA = 25°C
0.05
0.1
0.1
0.1
2.5
Offset Drift vs. Temperature1
16-lead SOIC_W
8-lead SOIC_IC
Offset Drift vs. VDD1
Gain Error1
Gain Error Drift vs. Temperature1
0.2
31.3
4
Initial at TA = 25°C
15.6
2
5
Gain Error Drift vs. VDD1
ANALOG INPUT
Input Voltage Range
−64
−50
+64
+50
mV
mV
V
µA
µA
µA
pF
Full-scale range
For specified performance
Input Common-Mode Voltage Range
Dynamic Input Current
−0.2 to +0.8
1
0.05
0.01
25
2
VIN+ = 50 mV, VIN− = 0 V
VIN+ = 0 V, VIN− = 0 V
DC Leakage Current
Input Capacitance
VIN+ or VIN− left floating
VIN+ = 1 kHz
DYNAMIC SPECIFICATIONS
Signal-to-Noise-and-Distortion Ratio (SINAD)1
SNR1
76.5
78.6
−78
82
82
−89
−97
dB
dB
dB
dB
Total Harmonic Distortion (THD)1
Peak Harmonic or Spurious-Free Dynamic
Range Noise (SFDR)1
Effective Number of Bits (ENOB)1
12.4
13
Bits
ISOLATION COMMON-MODE TRANSIENT
IMMUNITY (CMTI)1
Common-mode voltage (|VCM|) = 2 kV
Static and Dynamic
75
150
150
kV/µs
kV/µs
VDD2 = 5.5 V
VDD2 = 3.3 V
LOGIC INPUTS
CMOS with Schmitt trigger
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Current (IIN)
Input Capacitance (CIN)
LOGIC OUTPUTS
0.7 × VDD2
V
V
µA
pF
0.3 × VDD2
0.6
10
Output High Voltage (VOH)
Output Low Voltage (VOL)
VDD2 − 0.4 VDD2 − 0.2
0.2
V
V
Output current (IOUT) = −4 mA
IOUT = 4 mA
0.4
Rev. 0 | Page 3 of 22