Data Sheet
ADuM4470/ADuM4471/ADuM4472/ADuM4473/ADuM4474
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
Logic High Output Voltages
VOAH, VOBH
VOCH, VODH
,
VDDA − 0.3,
VISO − 0.3
3.3
V
IOx = −20 µA, VIx = VIxH
VDDA − 0.5,
VISO − 0.5
3.1
0.0
0.0
V
V
V
I
I
Ox = −4 mA, VIx = VIxH
Ox = 20 µA, VIx = VIxH
Logic Low Output Voltages
VOAL, VOBL
VOCL, VODL
,
0.1
0.4
IOx = 4 mA, VIx = VIxH
AC SPECIFICATIONS
ADuM447xARIZ
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL
Propagation Delay Skew
Channel-to-Channel Matching
ADuM447xCRIZ
PW
1000
ns
Mbps
ns
ns
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
1
tPLH, tPHL
PWD
tPSK
55
100
40
50
|
tPSKCD/tPSKOD
50
ns
Minimum Pulse Width
Maximum Data Rate
Propagation Delay
Pulse Width Distortion, |tPLH − tPHL
Change vs. Temperature
Propagation Delay Skew
Channel-to-Channel Matching,
Codirectional Channels
Channel-to-Channel Matching,
PW
40
ns
Mbps
ns
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
CL = 15 pF, CMOS signal levels
25
30
tPLH, tPHL
PWD
50
5
70
8
|
ns
ps/°C
ns
ns
tPSK
tPSKCD
15
8
tPSKCD
15
ns
CL = 15 pF, CMOS signal levels
Opposing Directional Channels
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity
at Logic High Output
Common-Mode Transient Immunity
at Logic Low Output
tR/tF
|CMH|
2.5
35
ns
kV/µs
CL = 15 pF, CMOS signal levels
VIx = VDDA or VISO, VCM = 1000 V,
transient magnitude = 800 V
VIx = 0 V or VISO, VCM = 1000 V,
transient magnitude = 800 V
25
25
|CML|
35
kV/µs
Mbps
Refresh Rate
fr
1.0
1 VDD1 is the power supply for the push-pull transformer.
2 VDDA is the power supply of Side 1 of the ADuM447x.
3 The contributions of supply current values for all four channels are combined at identical data rates.
4 The VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, the data I/O channels draw additional current
proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate can be calculated as described in the
Power Consumption section. The dynamic I/O channel load must be treated as an external load and included in the VISO power budget.
5 The power demands of the quiescent operation of the data channels were not separated from the power supply section. Efficiency includes the quiescent power
consumed by the I/O channels as part of the internal power consumption.
6 This current is available for driving external loads at the VISO output. All channels are simultaneously driven at a maximum data rate of 25 Mbps with full capacitive
load representing the maximum dynamic load conditions. Refer to the Power Consumption section for calculation of available current at less than the maximum
data rate.
Rev. 0 | Page 9 of 36