Datasheet > 驱动程序和接口 > MOSFET 驱动器> ADuM3221WARZ

ADuM3221WARZ

更新时间： 2024-02-29 10:00:12

品牌	Logo	应用领域
亚德诺 - ADI		外围驱动器栅极驱动程序和接口接口集成电路光电二极管栅极驱动
页数	文件大小	规格书
16页	614K
描述
Isolated, 4 A Dual-Channel Gate Driver

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ADuM3221WARZ 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	SOP, SOP8,.25
针数：	8	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.55	Is Samacsys：	N
内置保护：	TRANSIENT; OVER VOLTAGE; THERMAL; UNDER VOLTAGE	高边驱动器：	NO
接口集成电路类型：	BUFFER OR INVERTER BASED PERIPHERAL DRIVER	JESD-30 代码：	R-PDSO-G8
JESD-609代码：	e3	长度：	4.9 mm
湿度敏感等级：	3	功能数量：	2
端子数量：	8	最高工作温度：	125 °C
最低工作温度：	-40 °C	最大输出电流：	0.23 A
标称输出峰值电流：	4 A	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	260	筛选级别：	AEC-Q100
座面最大高度：	1.75 mm	最大压摆率：	17 mA
最大供电电压：	5.5 V	最小供电电压：	3 V
标称供电电压：	3.3 V	电源电压1-最大：	18 V
电源电压1-分钟：	4.5 V	电源电压1-Nom：	10 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子面层：	Matte Tin (Sn)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	30
断开时间：	0.72 µs	接通时间：	0.72 µs
宽度：	3.9 mm	Base Number Matches：	1

ADuM3221WARZ 数据手册

ADuM3220/ADuM3221

Data Sheet

APPLICATIONS INFORMATION

PC BOARD LAYOUT

THERMAL LIMITATIONS AND SWITCH LOAD

CHARACTERISTICS

The ADuM3220/ADuM3221 digital isolators require no exter-

nal interface circuitry for the logic interfaces. Power supply

bypassing is required at the input and output supply pins, as

shown in Figure 19. Use a small ceramic capacitor with a value

from 0.01 µF to 0.1 µF to provide a good high frequency bypass.

On the output power supply pin, V_DD2, it is recommended that a

10 µF capacitor also be added to provide the charge required to

drive the gate capacitance at the ADuM3220/ADuM3221 outputs.

On the output supply pin, the use of vias with the bypass capacitor

should be avoided, or multiple vias should be used to reduce the

inductance in the bypassing. The total lead length between both

ends of the smaller capacitor and the input or output power

supply pin should not exceed 20 mm.

For isolated gate drivers, the necessary separation between the

input and output circuits prevents the use of a single thermal pad

beneath the part; therefore, heat is dissipated mainly through

the package pins.

Package thermal dissipation limits the performance of switching

frequency vs. output load, as illustrated in Figure 8, which shows

the maximum load capacitance that can be driven with a 1 Ω series

gate resistor for different values of output voltage. For example,

this curve shows that a typical ADuM3220/ADuM3221 can drive

a large MOSFET with 120 nC gate charge at 8 V output (which is

equivalent to a 15 nF load) up to a frequency of about 300 kHz.

OUTPUT LOAD CHARACTERISTICS

DD1

DD2

The ADuM3220/ADuM3221 output signals depend on the

characteristics of the output load, which is typically an N-channel

MOSFET. The driver output response to an N-channel MOSFET

load can be modeled with a switch output resistance (R_SW), an

inductance due to the printed circuit board trace (L_TRACE), a series

gate resistor (R_GATE), and a gate-to-source capacitance (C_GS), as

shown in Figure 21.

GND

Figure 19. Recommended PCB Layout

PROPAGATION DELAY-RELATED PARAMETERS

Propagation delay is a parameter that describes the time it takes a

logic signal to propagate through a component. The propagation

delay to a logic low output can differ from the propagation delay

to a logic high output. The ADuM3220/ADuM3221 specify t_DLH

as the time between the input rising high logic threshold, V_IH,

and the output rising 10% threshold (see Figure 20). Likewise, the

falling propagation delay, t_DHL, is defined as the time between the

input falling logic low threshold, V_IL, and the output falling 90%

threshold. The rise and fall times are dependent on the loading

conditions and are not included in the propagation delay, as is

the industry standard for gate drivers.

GATE

ADuM3220/

ADuM3221

TRACE

Figure 21. RLC Model of the Gate of an N-Channel MOSFET

R_SWis the switch resistance of the internal ADuM3220/ADuM3221

driver output, which is about 1.5 Ω. R_GATEis the intrinsic gate

resistance of the MOSFET and any external series resistance. A

MOSFET that requires a 4 A gate driver has a typical intrinsic

gate resistance of about 1 Ω and a gate-to-source capacitance,

C_GS, from 2 nF to 10 nF. L_TRACEis the inductance of the printed

circuit board trace, typically a value of 5 nH or less for a well-

designed layout with a very short and wide connection from the

ADuM3220/ADuM3221 output to the gate of the MOSFET.

90%

OUTPUT

10%

The following equation defines the Q factor of the RLC circuit,

which indicates how the ADuM3220/ADuM3221 output responds

to a step change. For a well-damped output, Q is less than 1.

Adding a series gate resistor dampens the output response.

INPUT

t_DHL

t_DLH

t_R

t_F

L_TRACE

C_GS

Q =

(R_SW+ R_GATE

)

Figure 20. Propagation Delay Parameters

In Figure 5 and Figure 6, the ADuM3220/ADuM3221 output

waveforms for 10 V output are shown for a C_GSof 2 nF and 1 nF,

respectively. Note the ringing of the output in Figure 6 with C_GS

of 1 nF and a calculated Q factor of 1.5, where less than 1 is

desired for good damping.

Channel-to-channel matching refers to the maximum amount

that the propagation delay differs between channels within a

single ADuM3220/ADuM3221 component.

Propagation delay skew refers to the maximum amount that

the propagation delay differs between multiple ADuM3220/

ADuM3221 components operating under the same conditions.

Rev. C | Page 12 of 16

1...9 10 111213 14 15 16

中文翻译

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