ADuM2250/ADuM2251
APPLICATIONS INFORMATION
buffer on a bus segment implements a dual threshold scheme.
A bus segment is a portion of the I2C bus that is isolated from
other portions of the bus by galvanic isolation, bus extenders, or
level shifting buffers. Table 11 shows how multiple ADuM2250/
ADuM2251 components can coexist on a bus as long as two
Side 1 buffers are not connected to the same bus segment.
FUNCTIONAL DESCRIPTION
The ADuM2250/ADuM2251 interface on each side to I2C sig-
nals. Internally, the bidirectional I2C signals are split into two
unidirectional channels communicating in opposite directions
via dedicated iCoupler isolation channels. One channel of each
pair (the Side 1 input of each I/O pin in Figure 6) implements
a special input buffer and output driver that can differentiate
between externally generated inputs and its own output signals.
It only transfers externally generated input signals to the
corresponding Side 2 data or clock pin.
Table 11. ADuM225x Buffer Compatibility
Side 1
Side 2
No
Yes
Side 1
Side 2
Yes
Yes
Both the Side 1 and the Side 2 I2C pins are designed to interface
to an I2C bus operating in the 3.0 V to 5.5 V range. A logic low
on either side causes the corresponding I/O pin across the
coupler to be pulled low enough to comply with the logic low
threshold requirements of other I2C devices on the bus. Bus
contention and latch-up is avoided by guaranteeing that the
input low threshold at SDA1 or SCL1 is at least 50 mV less than
the output low signal at the same pin. This prevents an output
logic low at Side 1 being transmitted back to Side 2 and pulling
down the I2C bus by latching the state.
The output logic low levels are independent of the VDD1 and
DD2 voltages. The input logic low threshold at Side 1 is also
V
independent of VDD1. However, the input logic low threshold at
Side 2 is designed to be at 0.3 VDD2, consistent with I2C require-
ments. The Side 1 and Side 2 I/O pins have open-collector
outputs whose high levels are set via pull-up resistors to their
respective supply voltages.
GND
GND
1
2
1
2
3
4
5
16
15
14
13
12
ADuM2250
NC
V
NC
DD1
NC
Because the Side 2 logic levels/thresholds and drive capabilities
comply fully with standard I2C values, multiple ADuM2250/
ADuM2251 devices connected to a bus by their Side 2 pins
can communicate with each other and with other devices
having I2C compatibility as shown in Figure 7. Note the
distinction between I2C compatibility and I2C compliance.
I2C compatibility refers to situations in which the logic levels
or drive capability of a component do not necessarily meet the
requirements of the I2C specification but still allow the com-
ponent to communicate with an I2C-compliant device. I2C
compliance refers to situations in which the logic levels and
drive capability of a component fully meet the requirements
of the I2C specification.
V
DD2
NC
ENCODE
DECODE
ENCODE
DECODE
DECODE
ENCODE
DECODE
ENCODE
SDA
SDA
SCL
GND
2
1
1
1
SCL
2
6
7
8
11
10
9
NC
GND
NC
2
SYMBOL INDICATES A DUAL THRESHOLD INPUT BUFFER.
NC = NO CONNECT
Figure 6. ADuM2250 Block Diagram
Because the Side 1 pin has a modified output level/input thresh-
old, Side 1 of the ADuM2250/ADuM2251 can only communicate
with devices fully compliant with the I2C standard. In other
words, Side 2 of the ADuM2250/ADuM2251 is I2C-compliant
while Side 1 is only I2C-compatible.
The Side 1 I/O pins must not be connected to other I2C
buffers that implement a similar scheme of dual I/O threshold
detection. This latch-up prevention scheme is implemented in
several popular I2C level shifting and bus extension products
currently available from Analog Devices and other manufac-
turers. Care should be taken to review the data sheet of
potential I2C bus buffering products to ensure that only one
2
I C BUS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
ADuM2250
µCPU
OR
SECONDARY
BUS
V
V
DD1
DD2
SDA
SCK
SDA
SCK
2
1
1
2
SEGMENT
GND
1
GND
2
Figure 7. Typical Isolated I2C Interface Using ADuM2250
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