ADT7475
Table 41. Register 0x73 — Configuration Register 2 (Power−On Default = 0x00)
Bit No.
Mnemonic
R/W
Description
(Note 1)
[0:3]
[4]
RES
AVG
Reserved.
R/W
R/W
R/W
AVG = 1, averaging on the temperature and voltage measurements is turned off. This allows
measurements on each channel to be made much faster.
[5]
[6]
ATTN
ATTN = 1, the ADT7475 removes the attenuators from the V
used for other functions such as connecting up external sensors.
input. The V
input can be
CCP
CCP
CONV
CONV = 1, the ADT7475 is put into a single−channel ADC conversion mode. In this mode, the
ADT7475 can be made to read continuously from one input only, for example, Remote 1
temperature. The appropriate ADC channel is selected by writing to Bits [7:5] of TACH1
minimum high byte register (0x55).
Register 0x55, Bits [7:5]
000
001
010
011
100
101
110
111
Reserved
V
V
CCP
CC
Reserved
(3.3 V)
Reserved
Remote 1 temperature
Local temperature
Remote 2 temperature
[7]
SHDN
R/W
SHDN = 1, ADT7475 goes into shutdown mode. All PWM outputs assert low (or high depending
on state of the INV bit) to switch off all fans. The PWM current duty cycle registers read 0x00 to
indicate that the fans are not being driven.
1. These registers become read−only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.
Table 42. Register 0x74 — Interrupt Mask Register 1 (Power−On Default <7:0> = 0x00)
Bit No.
[1]
Mnemonic
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
V
CCP
V
V
= 1, masks SMBALERT for out−of−limit conditions on the V
channel.
CCP
CCP
[2]
V
CC
= 1, masks SMBALERT for out−of−limit conditions on the V channel.
CC CC
[4]
R1T
LT
R1T = 1, masks SMBALERT for out−of−limit conditions on the Remote 1 temperature channel.
LT = 1, masks SMBALERT for out−of−limit conditions on the local temperature channel.
R2T = 1, masks SMBALERT for out−of−limit conditions on the Remote 2 temperature channel.
[5]
[6]
R2T
OOL
[7]
OOL = 0, when one or more alerts are generated in Interrupt Status Register 2, assuming that
all the mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT is still asserted.
OOL = 1, when one or more alerts are generated in Interrupt Status Register 2, assuming that
all the mask bits in the Interrupt Mask Register 2 (0x75) = 1, SMBALERT is not asserted.
Table 43. Register 0x75 — Interrupt Mask Register 2 (Power−On Default <7:0> = 0x00)
Bit No.
[1]
Mnemonic
OVT
R/W
Read−only
R/W
Description
OVT = 1, masks SMBALERT for overtemperature THERM conditions.
FAN1 = 1, masks SMBALERT for a Fan 1 fault.
[2]
FAN1
FAN2
FAN3
F4P
[3]
R/W
FAN2 = 1, masks SMBALERT for a Fan 2 fault.
[4]
R/W
FAN3 = 1, masks SMBALERT for a Fan 3 fault.
[5]
R/W
F4P = 1, masks SMBALERT for a Fan 4 fault. If the TACH4 pin is being used as the THERM
input, this bit masks SMBALERT for a THERM timer event.
[6]
[7]
D1
D2
R/W
R/W
D1 = 1, masks SMBALERT for a diode open or short on a Remote 1 channel.
D2 = 1, masks SMBALERT for a diode open or short on a Remote 2 channel.
Table 44. Register 0x76 — Extended Resolution Register 1 (Note 1)
Bit No.
[3:2]
Mnemonic
R/W
R/W
R/W
Description
LSBs. Holds the 2 LSBs of the 10−bit V measurement.
V
CCP
V
V
CCP
CCP
[5:4]
V
CC
LSBs. Holds the 2 LSBs of the 10−bit V measurement.
CC CC
1. If this register is read, this register and the registers holding the MSB of each reading are frozen until read.
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