a
DSP Microcomputer
ADSP-2186
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
PERFORMANCE
POWER-DOWN
CONTROL
30 ns Instruction Cycle Tim e 33 MIPS Sustained
Perform ance
Single-Cycle Instruction Execution
Single-Cycle Context Sw itch
FULL MEMORY
MODE
MEMORY
PROGRAMMABLE
DATA ADDRESS
GENERATORS
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
8K 24
PROGRAM
MEMORY
8K 16
DATA
MEMORY
PROGRAM
SEQUENCER
DAG 1 DAG 2
3-Bus Architecture Allow s Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
Pow er-Dow n Mode Featuring Low CMOS Standby
Pow er Dissipation w ith 100 Cycle Recovery from
Pow er-Dow n Condition
PROGRAM MEMORY DATA
DATA MEMORY DATA
OR
EXTERNAL
DATA
BUS
Low Pow er Dissipation in Idle Mode
ARITHMETIC UNITS
ALU SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
INTERNAL
DMA
PORT
MAC
INTEGRATION
ADSP-2100 BASE
ARCHITECTURE
ADSP-2100 Fam ily Code Com patible, w ith Instruction
Set Extensions
HOST MODE
40K Bytes of On-Chip RAM, Configured as
8K Words On-Chip Program Mem ory RAM and
8K Words On-Chip Data Mem ory RAM
Dual Purpose Program Mem ory for Both Instruction
and Data Storage
Six External Interrupts
13 Program m able Flag Pins Provide Flexible System
Signaling
UART Em ulation through Softw are SPORT Reconfiguration
ICE-Port™* Em ulator Interface Supports Debugging
in Final System s
Independent ALU, Multiplier/ Accum ulator and Barrel
Shifter Com putational Units
Tw o Independent Data Address Generators
Pow erful Program Sequencer Provides
Zero Overhead Looping Conditional Instruction
Execution
Program m able 16-Bit Interval Tim er w ith Prescaler
100-Lead TQFP
GENERAL NO TE
T his data sheet represents production grade specifications for
the ADSP-2186 (5 V) processor. T his data sheet also contains
preliminary (x-grade) specifications for the new ADSP-2186
40 MHz processor.
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Mem ory (Mode Selectable)
4 MByte Byte Mem ory Interface for Storage of Data
Tables & Program Overlays
GENERAL D ESCRIP TIO N
T he ADSP-2186 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
T he ADSP-2186 combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
8-Bit DMA to Byte Mem ory for Transparent Program
and Data Mem ory Transfers (Mode Selectable)
I/ O Mem ory Interface w ith 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Program m able Mem ory Strobe and Separate I/ O Mem ory
Space Perm its “Glueless” System Design
(Mode Selectable)
Program m able Wait State Generation
Tw o Double-Buffered Serial Ports w ith Com panding
Hardw are and Autom atic Data Buffering
Autom atic Booting of On-Chip Program Mem ory from
Byte-Wide External Mem ory, e.g., EPROM, or
Through Internal DMA Port
T he ADSP-2186 integrates 40K bytes of on-chip memory con-
figured as 8K words (24-bit) of program RAM and 8K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equip-
ment. T he ADSP-2186 is available in 100-pin T QFP package.
In addition, the ADSP-2186 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
*ICE -P or t is a tr adem ar k of Analog D evices, Inc.
All tr adem ar ks ar e the pr oper ty of their r espective holder s.
REV. 0
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which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
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