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ADSP-BF534BBC-5A1 PDF预览

ADSP-BF534BBC-5A1

更新时间: 2024-11-25 03:16:43
品牌 Logo 应用领域
亚德诺 - ADI 时钟外围集成电路
页数 文件大小 规格书
60页 3350K
描述
IC 16-BIT, 50 MHz, OTHER DSP, PBGA182, MO-205AE, MBGA-182, Digital Signal Processor

ADSP-BF534BBC-5A1 数据手册

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Blackfin®  
Embedded Processor  
a
Preliminary Technical Data  
FEATURES  
ADSP-BF534  
Two Dual-Channel Memory DMA Controllers  
Memory Management Unit Providing Memory Protection  
Up to 500 MHz High-Performance Blackfin Processor  
Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video  
ALUs, 40-Bit Shifter  
RISC-Like Register and Instruction Model for Ease of  
Programming and Compiler-Friendly Support  
Advanced Debug, Trace, and Performance-Monitoring  
0.8 V to 1.2 V Core VDD with On-chip Voltage Regulation  
2.5 V and 3.3 V-Tolerant I/O with Specific 5 V-Tolerant Pins  
182-Ball MBGA and 208-Ball Sparse MBGA Packages  
Lead Bearing and Lead Free Package Choices  
PERIPHERALS  
Controller Area Network (CAN) 2.0B Interface  
Parallel Peripheral Interface (PPI), Supporting ITU-R 656  
Video Data Formats  
Two Dual-Channel, Full-Duplex Synchronous Serial Ports  
(SPORTs), Supporting Eight Stereo I2S Channels  
12 Peripheral DMAs  
Two Memory-to-Memory DMAs With External Request Lines  
Event Handler With 32 Interrupt Inputs  
Serial Peripheral Interface (SPI)-Compatible  
Two UARTs with IrDA® Support  
MEMORY  
132K Bytes of On-Chip Memory:  
16K Bytes of Instruction SRAM/Cache  
48K Bytes of Instruction SRAM  
32K Bytes of Data SRAM/Cache  
32K Bytes of Data SRAM  
Two-Wire Interface (TWI) Controller  
Eight 32-Bit Timer/Counters with PWM Support  
Real-Time Clock (RTC) and Watchdog Timer  
32-Bit Core Timer  
48 General-Purpose I/Os (GPIOs), 8 with High Current Drivers  
On-Chip PLL Capable of 1x to 63x Frequency Multiplication  
Debug/JTAG Interface  
4K Bytes of Scratchpad SRAM  
External Memory Controller with Glueless Support for  
SDRAM and Asynchronous 8/16-Bit Memories  
Flexible Booting Options from External Flash, SPI and TWI  
Memory or from SPI, TWI, and UART Host Devices  
EVENT  
JTAG TEST AND  
CONTROLLER/  
EMULATION  
WATCHDOG TIMER  
CORE TIMER  
RTC  
CAN  
VOLTAGE  
REGULATOR  
B
PORT  
TWI  
J
SPORT0  
L1  
L1  
MMU  
INSTRUCTION  
DATA  
MEMORY  
MEMORY  
SPORT1  
GPIO  
PORT  
G
PPI  
CORE / SYSTEM BUS INTERFACE  
UART 0-1  
GPIO  
PORT  
F
DMA  
CONTROLLER  
SPI  
TIMERS 0-7  
GPIO  
PORT  
H
BOOT ROM  
EXTERNAL PORT  
FLASH, SDRAM  
CONTROL  
Figure 1. Functional Block Diagram  
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.  
Rev. PrE  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel:781/329-4700  
Fax:781/461-3113  
www.analog.com  
© 2005 Analog Devices, Inc. All rights reserved.  

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