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ADSP-BF536_15

更新时间: 2024-11-25 01:11:39
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
68页 2394K
描述
Blackfin Embedded Processor

ADSP-BF536_15 数据手册

 浏览型号ADSP-BF536_15的Datasheet PDF文件第2页浏览型号ADSP-BF536_15的Datasheet PDF文件第3页浏览型号ADSP-BF536_15的Datasheet PDF文件第4页浏览型号ADSP-BF536_15的Datasheet PDF文件第5页浏览型号ADSP-BF536_15的Datasheet PDF文件第6页浏览型号ADSP-BF536_15的Datasheet PDF文件第7页 
Blackfin  
Embedded Processor  
ADSP-BF534/ADSP-BF536/ADSP-BF537  
FEATURES  
PERIPHERALS  
Up to 600 MHz high performance Blackfin processor  
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,  
40-bit shifter  
RISC-like register and instruction model for ease of  
programming and compiler-friendly support  
Advanced debug, trace, and performance monitoring  
Wide range of operating voltages (see Operating Conditions  
on Page 23)  
Qualified for Automotive Applications (see Automotive Prod-  
ucts on Page 66)  
Programmable on-chip voltage regulator  
182-ball and 208-ball CSP_BGA packages  
IEEE 802.3-compliant 10/100 Ethernet MAC (ADSP-BF536 and  
ADSP-BF537 only)  
Controller area network (CAN) 2.0B interface  
Parallel peripheral interface (PPI), supporting ITU-R 656  
video data formats  
2 dual-channel, full-duplex synchronous serial ports  
(SPORTs), supporting 8 stereo I2S channels  
12 peripheral DMAs, 2 mastered by the Ethernet MAC  
2 memory-to-memory DMAs with external request lines  
Event handler with 32 interrupt inputs  
Serial peripheral interface (SPI) compatible  
2 UARTs with IrDA support  
2-wire interface (TWI) controller  
MEMORY  
Eight 32-bit timer/counters with PWM support  
Real-time clock (RTC) and watchdog timer  
32-bit core timer  
48 general-purpose I/Os (GPIOs), 8 with high current drivers  
On-chip PLL capable of frequency multiplication  
Debug/JTAG interface  
Up to 132K bytes of on-chip memory  
Instruction SRAM/cache and instruction SRAM  
Data SRAM/cache plus additional dedicated data SRAM  
Scratchpad SRAM (see Table 1 on Page 3 for available  
memory configurations)  
External memory controller with glueless support for SDRAM  
and asynchronous 8-bit and 16-bit memories  
Flexible booting options from external flash, SPI and TWI  
memory or from SPI, TWI, and UART host devices  
Memory management unit providing memory protection  
VOLTAGE REGULATOR  
JTAG TEST AND EMULATION  
PERIPHERAL ACCESS BUS  
WATCHDOG TIMER  
RTC  
INTERRUPT  
CONTROLLER  
CAN  
B
TWI  
PORT J  
SPORT0  
SPORT1  
PPI  
L1  
L1  
DATA  
DMA  
CONTROLLER  
INSTRUCTION  
MEMORY  
GPIO  
PORT G  
MEMORY  
UART0-1  
SPI  
DMA CORE BUS  
EXTERNAL ACCESS BUS  
GPIO  
PORT F  
EXTERNAL PORT  
FLASH, SDRAM CONTROL  
TIMER7-0  
ETHERNET MAC  
(See Table 1)  
GPIO  
PORT H  
16  
BOOT ROM  
Figure 1. Functional Block Diagram  
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.  
Rev. J Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective companies.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2014 Analog Devices, Inc. All rights reserved.  
www.analog.com  

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