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ADSP-BF526KBCZ-4 PDF预览

ADSP-BF526KBCZ-4

更新时间: 2024-01-06 05:06:55
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器PC时钟
页数 文件大小 规格书
88页 2932K
描述
Blackfin Embedded Processor

ADSP-BF526KBCZ-4 技术参数

是否Rohs认证:符合生命周期:Obsolete
零件包装代码:BGA包装说明:12 X 12 MM, ROHS COMPLIANT, MO-195AJ, CSPBGA-289
针数:289Reach Compliance Code:compliant
HTS代码:8542.31.00.01风险等级:5.68
Is Samacsys:N其他特性:ALSO OPERATES AT 2.5 AND 3.3 V TYP
地址总线宽度:19桶式移位器:YES
位大小:32边界扫描:YES
最大时钟频率:50 MHz外部数据总线宽度:16
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:S-PBGA-B289长度:12 mm
低功率模式:YES端子数量:289
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:LFBGA
封装等效代码:BGA289,23X23,20封装形状:SQUARE
封装形式:GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.2,2.5/3.3 V认证状态:Not Qualified
座面最大高度:1.4 mm速度:400 MHz
子类别:Microprocessors最大供电电压:3.6 V
最小供电电压:1.7 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:BALL
端子节距:0.5 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:12 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

ADSP-BF526KBCZ-4 数据手册

 浏览型号ADSP-BF526KBCZ-4的Datasheet PDF文件第7页浏览型号ADSP-BF526KBCZ-4的Datasheet PDF文件第8页浏览型号ADSP-BF526KBCZ-4的Datasheet PDF文件第9页浏览型号ADSP-BF526KBCZ-4的Datasheet PDF文件第11页浏览型号ADSP-BF526KBCZ-4的Datasheet PDF文件第12页浏览型号ADSP-BF526KBCZ-4的Datasheet PDF文件第13页 
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527  
components as shown in Figure 4.  
unknown state where software, which would normally reset the  
timer, has stopped running due to an external noise condition  
or software error.  
RTXI  
RTXO  
If configured to generate a hardware reset, the watchdog timer  
resets both the core and the processor peripherals. After a reset,  
software can determine if the watchdog was the source of the  
hardware reset by interrogating a status bit in the watchdog  
timer control register.  
R1  
X1  
C1  
C2  
The timer is clocked by the system clock (SCLK), at a maximum  
frequency of fSCLK  
.
TIMERS  
SUGGESTED COMPONENTS:  
X1 = ECLIPTEK EC38J (THROUGH-HOLE PACKAGE) OR  
There are nine general-purpose programmable timer units in  
the processors. Eight timers have an external pin that can be  
configured either as a pulse width modulator (PWM) or timer  
output, as an input to clock the timer, or as a mechanism for  
measuring pulse widths and periods of external events. These  
timers can be synchronized to an external clock input to the sev-  
eral other associated PF pins, an external clock input to the  
PPI_CLK input pin, or to the internal SCLK.  
EPSON MC405 12 pF LOAD (SURFACE-MOUNT PACKAGE)  
C1 = 22 pF  
C2 = 22 pF  
R1 = 10 M:  
NOTE: C1 AND C2 ARE SPECIFIC TO CRYSTAL SPECIFIED FOR X1.  
CONTACT CRYSTAL MANUFACTURER FOR DETAILS. C1 AND C2  
SPECIFICATIONS ASSUME BOARD TRACE CAPACITANCE OF 3 pF.  
Figure 4. External Components for RTC  
The RTC peripheral has dedicated power supply pins so that it  
can remain powered up and clocked even when the rest of the  
processor is in a low power state. The RTC provides several pro-  
grammable interrupt options, including interrupt per second,  
minute, hour, or day clock ticks, interrupt on programmable  
stopwatch countdown, or interrupt at a programmed alarm  
time.  
The timer units can be used in conjunction with the two UARTs  
to measure the width of the pulses in the data stream to provide  
a software auto-baud detect function for the respective serial  
channels.  
The timers can generate interrupts to the processor core provid-  
ing periodic events for synchronization, either to the system  
clock or to a count of external signals.  
The 32.768 kHz input clock frequency is divided down to a 1 Hz  
signal by a prescaler. The counter function of the timer consists  
of four counters: a 60-second counter, a 60-minute counter, a  
24-hour counter, and an 32,768-day counter.  
In addition to the eight general-purpose programmable timers,  
a ninth timer is also provided. This extra timer is clocked by the  
internal processor clock and is typically used as a system tick  
clock for generation of operating system periodic interrupts.  
When enabled, the alarm function generates an interrupt when  
the output of the timer matches the programmed value in the  
alarm control register. There are two alarms: The first alarm is  
for a time of day. The second alarm is for a day and time of  
that day.  
UP/DOWN COUNTER AND THUMBWHEEL  
INTERFACE  
A 32-bit up/down counter is provided that can sense 2-bit  
quadrature or binary codes as typically emitted by industrial  
drives or manual thumb wheels. The counter can also operate in  
general-purpose up/down count modes. Then, count direction  
is either controlled by a level-sensitive input pin or by two edge  
detectors.  
The stopwatch function counts down from a programmed  
value, with one-second resolution. When the stopwatch is  
enabled and the counter underflows, an interrupt is generated.  
Like the other peripherals, the RTC can wake up the processor  
from sleep mode upon generation of any RTC wake-up event.  
Additionally, an RTC wakeup event can wake up the processor  
from deep sleep mode or cause a transition from the hibernate  
state.  
A third input can provide flexible zero marker support and can  
alternatively be used to input the push-button signal of thumb  
wheels. All three pins have a programmable debouncing circuit.  
An internal signal forwarded to the timer unit enables one timer  
to measure the intervals between count events. Boundary regis-  
ters enable auto-zero operation or simple system warning by  
interrupts when programmable count values are exceeded.  
WATCHDOG TIMER  
The processor includes a 32-bit timer that can be used to imple-  
ment a software watchdog function. A software watchdog can  
improve system availability by forcing the processor to a known  
state through generation of a hardware reset, nonmaskable  
interrupt (NMI), or general-purpose interrupt, if the timer  
expires before being reset by software. The programmer initial-  
izes the count value of the timer, enables the appropriate  
interrupt, then enables the timer. Thereafter, the software must  
reload the counter before it counts to zero from the pro-  
grammed value. This protects the system from remaining in an  
SERIAL PORTS  
The processors incorporate two dual-channel synchronous  
serial ports (SPORT0 and SPORT1) for serial and multiproces-  
sor communications. The SPORTs support the following  
features:  
• I2S capable operation.  
Rev. D  
|
Page 10 of 88 | July 2013  

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