5秒后页面跳转
捷配首页

Datasheet > 微控制器和处理器 > 数字信号处理器> ADSP-BF526KBCZ-4
ADSP-BF526KBCZ-4 PDF预览

ADSP-BF526KBCZ-4

更新时间： 2024-01-31 10:45:17
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器PC时钟
页数 文件大小 规格书
88页 2932K
描述
Blackfin Embedded Processor

阅读下载

获取价格

ADSP-BF526KBCZ-4 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：BGA包装说明：12 X 12 MM, ROHS COMPLIANT, MO-195AJ, CSPBGA-289
针数：289Reach Compliance Code：compliant
HTS代码：8542.31.00.01风险等级：5.68
Is Samacsys：N其他特性：ALSO OPERATES AT 2.5 AND 3.3 V TYP
地址总线宽度：19桶式移位器：YES
位大小：32边界扫描：YES
最大时钟频率：50 MHz外部数据总线宽度：16
格式：FIXED POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PBGA-B289长度：12 mm
低功率模式：YES端子数量：289
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：LFBGA
封装等效代码：BGA289,23X23,20封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE, FINE PITCH峰值回流温度（摄氏度）：NOT SPECIFIED
电源：1.2,2.5/3.3 V认证状态：Not Qualified
座面最大高度：1.4 mm速度：400 MHz
子类别：Microprocessors最大供电电压：3.6 V
最小供电电压：1.7 V标称供电电压：1.8 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：BALL
端子节距：0.5 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：12 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

ADSP-BF526KBCZ-4 数据手册

 浏览型号ADSP-BF526KBCZ-4的Datasheet PDF文件第5页浏览型号ADSP-BF526KBCZ-4的Datasheet PDF文件第6页浏览型号ADSP-BF526KBCZ-4的Datasheet PDF文件第7页浏览型号ADSP-BF526KBCZ-4的Datasheet PDF文件第9页浏览型号ADSP-BF526KBCZ-4的Datasheet PDF文件第10页浏览型号ADSP-BF526KBCZ-4的Datasheet PDF文件第11页 
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527  
Table 3. System Interrupt Controller (SIC) (Continued)  
General Purpose  
Default  
Core Interrupt ID  
Peripheral Interrupt Event  
OTP Memory Interrupt  
GP Counter  
Interrupt (at RESET) Peripheral Interrupt ID  
SIC Registers  
IVG11  
IVG11  
IVG11  
IVG11  
IVG11  
IVG11  
IVG12  
IVG12  
IVG12  
IVG12  
IVG12  
IVG12  
IVG12  
IVG12  
IVG12  
IVG12  
IVG13  
IVG13  
IVG13  
IVG13  
IVG13  
IVG7  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
36  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
49  
50  
51  
52  
53  
54  
55  
4
4
4
4
4
4
5
5
5
5
5
5
5
5
5
5
6
6
6
6
6
0
0
0
0
3
3
3
3
3
IAR3 IMASK0, ISR0, IWR0  
IAR3 IMASK0, ISR0, IWR0  
IAR3 IMASK0, ISR0, IWR0  
IAR3 IMASK0, ISR0, IWR0  
IAR3 IMASK0, ISR0, IWR0  
IAR3 IMASK0, ISR0, IWR0  
IAR4 IMASK1, ISR1, IWR1  
IAR4 IMASK1, ISR1, IWR1  
IAR4 IMASK1, ISR1, IWR1  
IAR4 IMASK1, ISR1, IWR1  
IAR4 IMASK1, ISR1, IWR1  
IAR4 IMASK1, ISR1, IWR1  
IAR4 IMASK1, ISR1, IWR1  
IAR4 IMASK1, ISR1, IWR1  
IAR5 IMASK1, ISR1, IWR1  
IAR5 IMASK1, ISR1, IWR1  
IAR5 IMASK1, ISR1, IWR1  
IAR5 IMASK1, ISR1, IWR1  
IAR5 IMASK1, ISR1, IWR1  
IAR5 IMASK1, ISR1, IWR1  
IAR5 IMASK1, ISR1, IWR1  
IAR5 IMASK1, ISR1, IWR1  
IAR6 IMASK1, ISR1, IWR1  
IAR6 IMASK1, ISR1, IWR1  
IAR6 IMASK1, ISR1, IWR1  
IAR6 IMASK1, ISR1, IWR1  
IAR6 IMASK1, ISR1, IWR1  
IAR6 IMASK1, ISR1, IWR1  
IAR6 IMASK1, ISR1, IWR1  
IAR6 IMASK1, ISR1, IWR1  
DMA Channel 1 (MAC RX/HOSTDP)  
Port H Interrupt A  
DMA Channel 2 (MAC TX/NFC)  
Port H Interrupt B  
Timer 0  
Timer 1  
Timer 2  
Timer 3  
Timer 4  
Timer 5  
Timer 6  
Timer 7  
Port G Interrupt A  
Port G Interrupt B  
MDMA Stream 0  
MDMA Stream 1  
Software Watchdog Timer  
Port F Interrupt A  
Port F Interrupt B  
SPI Status  
NFC Status  
IVG7  
HOSTDP Status  
Host Read Done  
Reserved  
IVG7  
IVG7  
IVG10  
IVG10  
IVG10  
IVG10  
IVG10  
USB_INT0 Interrupt  
USB_INT1 Interrupt  
USB_INT2 Interrupt  
USB_DMAINT Interrupt  
Event Control  
The processor provides a very flexible mechanism to control the  
processing of events. In the CEC, three registers are used to  
coordinate and control events. Each register is 16 bits wide.  
written while in supervisor mode. (Note that general-  
purpose interrupts can be globally enabled and disabled  
with the STI and CLI instructions, respectively.)  
• CEC interrupt latch register (ILAT) — Indicates when  
events have been latched. The appropriate bit is set when  
the processor has latched the event and cleared when the  
event has been accepted into the system. This register is  
updated automatically by the controller, but it may be writ-  
ten only when its corresponding IMASK bit is cleared.  
• CEC interrupt pending register (IPEND) — The IPEND  
register keeps track of all nested events. A set bit in the  
IPEND register indicates the event is currently active or  
nested at some level. This register is updated automatically  
by the controller but may be read while in supervisor mode.  
The SIC allows further control of event processing by providing  
three pairs of 32-bit interrupt control and status registers. Each  
register contains a bit corresponding to each of the peripheral  
interrupt events shown in Table 3 on Page 7.  
• CEC interrupt mask register (IMASK) — Controls the  
masking and unmasking of individual events. When a bit is  
set in the IMASK register, that event is unmasked and is  
processed by the CEC when asserted. A cleared bit in the  
IMASK register masks the event, preventing the processor  
from servicing the event even though the event may be  
latched in the ILAT register. This register may be read or  
• SIC interrupt mask registers (SIC_IMASKx) — Control the  
masking and unmasking of each peripheral interrupt event.  
When a bit is set in these registers, that peripheral event is  
Rev. D  
| Page 8 of 88 | July 2013  
1...567891011...88

下载PDF

与ADSP-BF526KBCZ-4相关器件

型号 品牌 描述 获取价格 数据表
ADSP-BF526KBCZ4C2X ADI IC OTHER DSP, PBGA289, 12 X 12 MM, ROHS COMPLIANT, BC-289-2, CSP_BGA-289, Digital Signal P

获取价格
ADSP-BF526KBCZ-4X ADI IC OTHER DSP, Digital Signal Processor

获取价格
ADSP-BF527 ADI Blackfin Embedded Processor

获取价格
ADSP-BF527_15 ADI Blackfin Embedded Processor

获取价格
ADSP-BF527BBCZ-5A ADI Blackfin Embedded Processor

获取价格
ADSP-BF527BBCZ-5AX ADI IC 0-BIT, 133 MHz, OTHER DSP, PBGA208, 17 X 17 MM, MO-205AM, CSPBGA-289, Digital Signal Pr

获取价格

与ADSP-BF526KBCZ-4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证