ADSP-2185
wide variety of framed or frameless data transmit and receive
modes of operation.
T he internal result (R) bus connects the computational units so
the output of any unit may be the input of any unit on the next
cycle.
Each port can generate an internal programmable serial clock or
accept an external serial clock.
A powerful program sequencer and two dedicated data address
generators ensure efficient delivery of operands to these compu-
tational units. T he sequencer supports conditional jumps, sub-
routine calls and returns in a single cycle. With internal loop
counters and loop stacks, the ADSP-2185 executes looped code
with zero overhead; no explicit jump instructions are required to
maintain loops.
T he ADSP-2185 provides up to 13 general-purpose flag pins.
T he data input and output pins on SPORT 1 can be alternatively
configured as an input flag and an output flag. In addition,
eight flags are programmable as inputs or outputs, and three
flags are always outputs.
A programmable interval timer generates periodic interrupts. A
16-bit count register (T COUNT ) decrements every n processor
cycle, where n is a scaling value stored in an 8-bit register
(T SCALE). When the value of the count register reaches zero,
an interrupt is generated and the count register is reloaded from
a 16-bit period register (T PERIOD).
T wo data address generators (DAGs) provide addresses for
simultaneous dual operand fetches from data memory and pro-
gram memory. Each DAG maintains and updates four address
pointers. Whenever the pointer is used to access data (indirect
addressing), it is post-modified by the value of one of four pos-
sible modify registers. A length value may be associated with
each pointer to implement automatic modulo addressing for
circular buffers.
Ser ial P or ts
T he ADSP-2185 incorporates two complete synchronous serial
ports (SPORT 0 and SPORT 1) for serial communications and
multiprocessor communication.
Efficient data transfer is achieved with the use of five internal
buses:
Here is a brief list of the capabilities of the ADSP-2185 SPORTs.
For additional information on Serial Ports, refer to the ADSP-
2100 Family User’s Manual.
• Program Memory Address (PMA) Bus
• Program Memory Data (PMD) Bus
• Data Memory Address (DMA) Bus
• Data Memory Data (DMD) Bus
• Result (R) Bus
• SPORT s are bidirectional and have a separate, double-buff-
ered transmit and receive section.
• SPORT s can use an external serial clock or generate their own
serial clock internally.
T he two address buses (PMA and DMA) share a single external
address bus, allowing memory to be expanded off-chip, and the
two data buses (PMD and DMD) share a single external data
bus. Byte memory space and I/O memory space also share the
external buses.
• SPORT s have independent framing for the receive and trans-
mit sections. Sections run in a frameless mode or with frame
synchronization signals internally or externally generated.
Frame sync signals are active high or inverted, with either of
two pulse widths and timings.
Program memory can store both instructions and data, permit-
ting the ADSP-2185 to fetch two operands in a single cycle, one
from program memory and one from data memory. T he ADSP-
2185 can fetch an operand from program memory and the next
instruction in the same cycle.
• SPORT s support serial data word lengths from 3 to 16 bits
and provide optional A-law and µ-law companding according
to CCIT T recommendation G.711.
When configured in host mode, the ADSP-2185 has a 16-bit
Internal DMA port (IDMA port) for connection to external
systems. T he IDMA port is made up of 16 data/address pins
and five control pins. T he IDMA port provides transparent,
direct access to the DSPs on-chip program and data RAM.
• SPORT receive and transmit sections can generate unique
interrupts on completing a data word transfer.
• SPORT s can receive and transmit an entire circular buffer of
data with only one overhead cycle per data word. An interrupt
is generated after a data buffer transfer.
An interface to low cost byte-wide memory is provided by the
Byte DMA port (BDMA port). T he BDMA port is bidirectional
and can directly address up to four megabytes of external RAM
or ROM for off-chip storage of program overlays or data tables.
• SPORT 0 has a multichannel interface to selectively receive
and transmit a 24 or 32 word, time-division multiplexed,
serial bitstream.
• SPORT 1 can be configured to have two external interrupts
(IRQ0 and IRQ1) and the Flag In and Flag Out signals. T he
internally generated serial clock may still be used in this con-
figuration.
T he byte memory and I/O memory space interface supports
slow memories and I/O memory-mapped peripherals with
programmable wait state generation. External devices can
gain control of external buses with bus request/grant signals
(BR, BGH and BG). One execution mode (Go Mode) allows
the ADSP-2185 to continue running from on-chip memory.
Normal execution mode requires the processor to halt while
buses are granted.
P IN D ESCRIP TIO NS
T he ADSP-2185 will be available in a 100-lead T QFP package.
In order to maintain maximum functionality and reduce pack-
age size and pin count, some serial port, programmable flag,
interrupt and external bus pins have dual, multiplexed function-
ality. T he external bus pins are configured during RESET only,
while serial port pins are software configurable during program
execution. Flag and interrupt functionality is retained concur-
rently on multiplexed pins. In cases where pin functionality is
reconfigurable, the default state is shown in plain text; alternate
functionality is shown in italics.
T he ADSP-2185 can respond to eleven interrupts. T here can be
up to six external interrupts (one edge-sensitive, two level-sensitive
and three configurable) and seven internal interrupts generated
by the timer, the serial ports (SPORT s), the Byte DMA port
and the power-down circuitry. T here is also a master RESET
signal. T he two serial ports provide a complete synchronous
serial interface with optional companding in hardware and a
REV. 0
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