ADSP-2185
T he EZ-ICE®* performs a full range of functions, including:
Fabricated in a high speed, double metal, low power, 0.5 µm
CMOS process, the ADSP-2185 operates with a 30 ns instruc-
tion cycle time. Every instruction can execute in a single proces-
sor cycle.
• In-target operation
• Up to 20 breakpoints
• Single-step or full-speed operation
• Registers and memory values can be examined and altered
• PC upload and download functions
• Instruction-level emulation of program booting and execution
• Complete assembly and disassembly of instructions
• C source-level debugging
See Designing An EZ-ICE®*-Compatible T arget System in the
ADSP-2100 Family EZ-Tools Manual (ADSP-2181 sections) as
well as the T arget Board Connector for EZ-ICE®* Probe sec-
tion of this data sheet for the exact specifications of the EZ-ICE®*
target board connector.
T he ADSP-2185’s flexible architecture and comprehensive
instruction set allow the processor to perform multiple opera-
tions in parallel. In one processor cycle the ADSP-2185 can:
• generate the next program address
• fetch the next instruction
• perform one or two data moves
• update one or two data address pointers
• perform a computational operation
T his takes place while the processor continues to:
• receive and transmit data through the two serial ports
• receive and/or transmit data through the internal DMA port
• receive and/or transmit data through the byte DMA port
• decrement timer
Additional Infor m ation
T his data sheet provides a general overview of ADSP-2185
functionality. For additional information on the architecture and
instruction set of the processor, refer to the ADSP-2100 Family
User’s Manual. For more information about the development
tools, refer to the ADSP-2100 Family Development Tools Data
Sheet.
D evelopm ent System
T he ADSP-2100 Family Development Software, a complete set
of tools for software and hardware system development, sup-
ports the ADSP-2185. T he System Builder provides a high level
method for defining the architecture of systems under develop-
ment. T he Assembler has an algebraic syntax that is easy to
program and debug. T he Linker combines object files into an
executable file. The Simulator provides an interactive instruction-
level simulation with a reconfigurable user interface to display
different portions of the hardware environment. A PROM
Splitter generates PROM programmer compatible files. T he
C Compiler, based on the Free Software Foundation’s GNU
C Compiler, generates ADSP-2185 assembly source code. T he
source code debugger allows programs to be corrected in the
C environment. T he Runtime Library includes over 100 ANSI-
standard mathematical and DSP-specific functions.
ARCH ITECTURE O VERVIEW
T he ADSP-2185 instruction set provides flexible data moves
and multifunction (one or two data moves with a computation)
instructions. Every instruction can be executed in a single pro-
cessor cycle. T he ADSP-2185 assembly language uses an alge-
braic syntax for ease of coding and readability. A comprehensive
set of development tools supports program development.
POWER-DOWN
CONTROL
FULL MEMORY
MODE
MEMORY
PROGRAMMABLE
DATA ADDRESS
GENERATORS
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
PROGRAM
MEMORY
DATA
MEMORY
PROGRAM
SEQUENCER
DAG 1 DAG 2
T he EZ-KIT Lite is a hardware/software kit offering a complete
development environment for the entire ADSP-21xx family: an
ADSP-218x based evaluation board with PC monitor software
plus Assembler, Linker, Simulator and PROM Splitter software.
T he ADSP-21xx EZ-KIT Lite is a low cost, easy to use hard-
ware platform on which you can quickly get started with your
DSP software design. T he EZ-KIT Lite includes the following
features:
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
DATA MEMORY DATA
OR
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
INTERNAL
DMA
PORT
MAC
• 33 MHz ADSP-2181
ADSP-2100 BASE
ARCHITECTURE
HOST MODE
• Full 16-bit Stereo Audio I/O with AD1847 SoundPort®* Codec
• RS-232 Interface to PC with Windows® 3.1 Control Software
• Stand-Alone Operation with Socketed EPROM
• EZ-ICE®* Connector for Emulator Control
• DSP Demo Programs
Figure 1. Block Diagram
Figure 1 is an overall block diagram of the ADSP-2185. T he
processor contains three independent computational units: the
ALU, the multiplier/accumulator (MAC) and the shifter. T he
computational units process 16-bit data directly and have provi-
sions to support multiprecision computations. T he ALU per-
forms a standard set of arithmetic and logic operations; division
primitives are also supported. T he MAC performs single-cycle
multiply, multiply/add and multiply/subtract operations with 40
bits of accumulation. T he shifter performs logical and arith-
metic shifts, normalization, denormalization and derive expo-
nent operations.
T he ADSP-218x EZ-ICE®* Emulator aids in the hardware
debugging of an ADSP-2185 system. T he emulator consists of
hardware, host computer resident software, and the target board
connector. T he ADSP-2185 integrates on-chip emulation sup-
port with a 14-pin ICE-PORT ™* interface. T his interface pro-
vides a simpler target board connection that requires fewer
mechanical clearance considerations than other ADSP-2100
Family EZ-ICE®*s. The ADSP-2185 device need not be removed
from the target system when using the EZ-ICE®*, nor are any
adapters needed. Due to the small footprint of the EZ-ICE®*
connector, emulation can be supported in final board designs.
T he shifter can be used to efficiently implement numeric
format control including multiword and block floating-point
representations.
*All trademarks are the property of their respective holders.
*EZ-ICE and SoundPORT are registered trademarks of Analog Devices, Inc.
REV. 0
–2–
5秒后页面跳转
NTC热敏电阻与PTC热敏电阻的应用原理及应用范围
GTO与普通晶闸管相比为什么可以自关断？为什么普通晶闸管不能呢？从GTO原理、应用范围带你了解原因及推荐型号
LF353数据手册解读：特性、应用、封装、引脚说明、电气参数及替换型号推荐
A4950资料手册解读：特性、应用、封装、引脚功能、电气参数及代换型号
微信公众号
抖音公众号
浙公网安备 33010502006866号 浙ICP备10014259号-119
营业执照ICP证
技术参数
数据手册
如果您发现信息不准确，
