Datasheet > 微控制器和处理器 > 数字信号处理器> ADSP-2183KST-160

ADSP-2183KST-160

更新时间： 2024-01-18 19:33:12

品牌	Logo	应用领域
亚德诺 - ADI		微控制器和处理器外围集成电路数字信号处理器电脑时钟
页数	文件大小	规格书
31页	251K
描述
DSP Microcomputer

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技术参数
数据手册
替代型号

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ADSP-2183KST-160 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	QFP, QFP128,.63X.87,20	Reach Compliance Code：	unknown
ECCN代码：	3A991.A.2	HTS代码：	8542.31.00.01
风险等级：	5.92	位大小：	16
格式：	FIXED POINT	JESD-30 代码：	R-PQFP-G128
JESD-609代码：	e0	端子数量：	128
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP128,.63X.87,20	封装形状：	RECTANGULAR
封装形式：	FLATPACK	电源：	3.3 V
认证状态：	Not Qualified	RAM（字数）：	16384
子类别：	Digital Signal Processors	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	Base Number Matches：	1

ADSP-2183KST-160 数据手册

浏览型号ADSP-2183KST-160的Datasheet PDF文件第10页

ADSP-2183

There are 16,352 words of memory accessible internally when

the DMOVLAY register is set to 0. When DMOVLAY is set to

something other than 0, external accesses occur at addresses

0x0000 through 0x1FFF. The external address is generated as

shown in Table III.

The CMS pin functions like the other memory select signals,

with the same timing and bus request logic. A 1 in the enable bit

causes the assertion of the CMS signal at the same time as the

selected memory select signal. All enable bits, except the BMS

bit, default to 1 at reset.

Byte Memory

Table III.

The byte memory space is a bidirectional, 8-bit-wide, external

memory space used to store programs and data. Byte memory is

accessed using the BDMA feature. The byte memory space

consists of 256 pages, each of which is 16K × 8.

DMOVLAY Memory A13

A12:0

Internal

Not Applicable Not Applicable

External

Overlay 1

13 LSBs of Address

Between 0x0000

and 0x1FFF

The byte memory space on the ADSP-2183 supports read and

write operations as well as four different data formats. The byte

memory uses data bits 15:8 for data. The byte memory uses

data bits 23:16 and address bits 13:0 to create a 22-bit address.

This allows up to a 4 meg × 8 (32 megabit) ROM or RAM to be

used without glue logic. All byte memory accesses are timed by

the BMWAIT register.

External

13 LSBs of Address

Between 0x0000

and 0x1FFF

Overlay 2

Byte Memory DMA (BDMA)

This organization allows for two external 8K overlays using only

the normal 14 address bits.

The Byte memory DMA controller allows loading and storing of

program instructions and data using the byte memory space.

The BDMA circuit is able to access the byte memory space,

while the processor is operating normally and steals only one

DSP cycle per 8-, 16- or 24-bit word transferred.

All internal accesses complete in one cycle. Accesses to external

memory are timed using the wait states specified by the DWAIT

I/O Space

The BDMA circuit supports four different data formats which

are selected by the BTYPE register field. The appropriate num-

ber of 8-bit accesses are done from the byte memory space to

build the word size selected. Table V shows the data formats

supported by the BDMA circuit.

The ADSP-2183 supports an additional external memory space

called I/O space. This space is designed to support simple con-

nections to peripherals or to bus interface ASIC data registers.

I/O space supports 2048 locations. The lower eleven bits of the

external address bus are used; the upper 3 bits are undefined.

Two instructions were added to the core ADSP-2100 Family

instruction set to read from and write to I/O memory space.

The I/O space also has four dedicated 3-bit wait state regis-

ters, IOWAIT0-3, which specify up to seven wait states to be

automatically generated for each of four regions. The wait states

act on address ranges as shown in Table IV.

Table V.

Internal

Memory Space

BTYPE

Word Size

Alignment

Program Memory

Data Memory

Full Word

MSBs

Table IV.

LSBs

Address Range

Wait State Register

Unused bits in the 8-bit data memory formats are filled with 0s.

The BIAD register field is used to specify the starting address

for the on-chip memory involved with the transfer. The 14-bit

BEAD register specifies the starting address for the external byte

memory space. The 8-bit BMPAGE register specifies the start-

ing page for the external byte memory space. The BDIR register

field selects the direction of the transfer. Finally the 14-bit

BWCOUNT register specifies the number of DSP words to

transfer and initiates the BDMA circuit transfers.

0x000–0x1FF

0x200–0x3FF

0x400–0x5FF

0x600–0x7FF

IOWAIT0

IOWAIT1

IOWAIT2

IOWAIT3

Composite Memory Select (CMS)

The ADSP-2183 has a programmable memory select signal that

is useful for generating memory select signals for memories

mapped to more than one space. The CMS signal is generated

to have the same timing as each of the individual memory select

signals (PMS, DMS, BMS, IOMS) but can combine their

functionality.

BDMA accesses can cross page boundaries during sequential

addressing. A BDMA interrupt is generated on the completion

of the number of transfers specified by the BWCOUNT register.

The BWCOUNT register is updated after each transfer so it can

be used to check the status of the transfers. When it reaches

zero, the transfers have finished and a BDMA interrupt is gener-

ated. The BMPAGE and BEAD registers must not be accessed

by the DSP during BDMA operations.

When set, each bit in the CMSSEL register causes the CMS

signal to be asserted when the selected memory select is as-

serted. For example, to use a 32K word memory to act as both

program and data memory, set the PMS and DMS bits in the

CMSSEL register and use the CMS pin to drive the chip

select of the memory; use either DMS or PMS as the additional

address bit.

The source or destination of a BDMA transfer will always be

on-chip program or data memory, regardless of the values of

MMAP, PMOVLAY or DMOVLAY.

–8–

REV. C

1...5 6 789 10 11...31

中文翻译

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ADSP-2183KST-160 替代型号

型号	品牌	替代类型	描述	数据表
ADSP-2183KST-160	ADI	当前型号	DSP Microcomputer
ADSP-2183BSTZ-160	ADI	功能相似	16-bit, 52 MIPS, 3.3 v, 2 serial ports, host port, 80 KB RAM
ADSP-2183KSTZ-160	ADI	完全替代	DSP Microcomputer
ADSP-2183BST-160	ADI	完全替代	DSP Microcomputer

与ADSP-2183KST-160相关器件

型号	品牌	获取价格	描述	数据表
ADSP-2183KST-210	ROCHESTER	获取价格	24-BIT, 26.32 MHz, OTHER DSP, PQFP128, METRIC, PLASTIC, TQFP-128
ADSP-2183KST-210	ADI	获取价格	DSP Microcomputer
ADSP-2183KST-210X	ETC	获取价格	16-Bit Digital Signal Processor
ADSP-2183KSTZ-115	ROCHESTER	获取价格	24-BIT, 14.4 MHz, OTHER DSP, PQFP128, METRIC, PLASTIC, TQFP-128
ADSP-2183KSTZ-133	ADI	获取价格	IC 24-BIT, 16.67 MHz, OTHER DSP, PQFP128, METRIC, PLASTIC, TQFP-128, Digital Signal Proces
ADSP-2183KSTZ-160	ADI	获取价格	DSP Microcomputer
ADSP-2183KSTZ-160	ROCHESTER	获取价格	24-BIT, 20 MHz, OTHER DSP, PQFP128, METRIC, PLASTIC, TQFP-128
ADSP2184	ADI	获取价格	DSP Microcomputer
ADSP-2184	ADI	获取价格	DSP Microcomputer
ADSP-2184BST-160	ADI	获取价格	DSP Microcomputer

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