ADSP-2181
When the IDLE (n) instruction is used, it effectively slows down
the processor’s internal clock and thus its response time to in-
coming interrupts. T he one-cycle response time of the standard
idle state is increased by n, the clock divisor. When an enabled
interrupt is received, the ADSP-2181 will remain in the idle
state for up to a maximum of n processor cycles (n = 16, 32, 64
or 128) before resuming normal operation.
If an external clock is used, it should be a T T L-compatible
signal running at half the instruction rate. T he signal is con-
nected to the processor’s CLKIN input. When an external clock
is used, the XT AL input must be left unconnected.
T he ADSP-2181 uses an input clock with a frequency equal to
half the instruction rate; a 20.00 MHz input clock yields a 25 ns
processor cycle (which is equivalent to 40 MHz). Normally,
instructions are executed in a single processor cycle. All device
timing is relative to the internal instruction clock rate, which is
indicated by the CLKOUT signal when enabled.
When the IDLE (n) instruction is used in systems that have an
externally generated serial clock (SCLK), the serial clock rate
may be faster than the processor’s reduced internal clock rate.
Under these conditions, interrupts must not be generated at a
faster rate than can be serviced, due to the additional time the
processor takes to come out of the idle state (a maximum of n
processor cycles).
Because the ADSP-2181 includes an on-chip oscillator circuit,
an external crystal may be used. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors connected
as shown in Figure 3. Capacitor values are dependent on crystal
type and should be specified by the crystal manufacturer. A
parallel-resonant, fundamental frequency, microprocessor-grade
crystal should be used.
SYSTEM INTERFACE
Figure 2 shows a typical basic system configuration with the
ADSP-2181, two serial devices, a byte-wide EPROM, and op-
tional external program and data overlay memories. Program-
mable wait state generation allows the processor to connect
easily to slow peripheral devices. T he ADSP-2181 also provides
four external interrupts and two serial ports or six external inter-
rupts and one serial port.
A clock output (CLKOUT ) signal is generated by the processor
at the processor’s cycle rate. T his can be enabled and disabled
by the CLKODIS bit in the SPORT 0 Autobuffer Control
Register.
ADSP-2181
CLKIN
A
D
13-0
1/2x CLOCK
OR
CLKIN
XTAL
CLKOUT
14
ADDR13-0
XTAL
CRYSTAL
A0-A21
23-16
DSP
FL0-2
PF0-7
BYTE
MEMORY
D
15-8
24
DATA23-0
DATA
IRQ2
IRQE
IRQL0
IRQL1
CS
BMS
A
Figure 3. External Crystal Connections
10-0
RD
WR
ADDR
DATA
D
23-8
SPORT1
SCLK1
RFS1 OR IRQ0
TFS1 OR IRQ1
DT1 OR FO
DR1 OR FI
Reset
I/O SPACE
(PERIPHERALS)
2048 LOCATIONS
T he RESET signal initiates a master reset of the ADSP-2181.
T he RESET signal must be asserted during the power-up se-
quence to assure proper initialization. RESET during initial
power-up must be held long enough to allow the internal clock
to stabilize. If RESET is activated any time after power-up, the
clock continues to run and does not require stabilization time.
SERIAL
DEVICE
CS
IOMS
A
13-0
ADDR
DATA
OVERLAY
MEMORY
D
SPORT0
SCLK0
RFS0
TFS0
DT0
23-0
SERIAL
DEVICE
TWO 8K
PM SEGMENTS
PMS
DMS
CMS
DR0
TWO 8K
DM SEGMENTS
IDMA PORT
BR
BG
BGH
T he power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid VDD is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum of
2000 CLKIN cycles ensures that the PLL has locked, but does
not include the crystal oscillator start-up time. During this
power-up sequence the RESET signal should be held low. On
any subsequent resets, the RESET signal must meet the mini-
IRD
SYSTEM
INTERFACE
OR
IWR
IS
PWD
IAL
IACK
IAD15-0
CONTROLLER
PWDACK
16
Figure 2. ADSP-2181 Basic System Configuration
Clock Signals
T he ADSP-2181 can be clocked by either a crystal or a T T L-
compatible clock signal.
mum pulse width specification, tRSP
.
T he CLKIN input cannot be halted, changed during operation
or operated below the specified frequency during normal opera-
tion. T he only exception is while the processor is in the power-
down state. For additional information, refer to Chapter 9,
ADSP-2100 Family User’s Manual, Third Edition, for detailed
information on this power-down feature.
T he RESET input contains some hysteresis; however, if you use
an RC circuit to generate your RESET signal, the use of an
external Schmidt trigger is recommended.
T he master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts and clears the MST AT
register. When RESET is released, if there is no pending bus
request and the chip is configured for booting (MMAP = 0), the
boot-loading sequence is performed. T he first instruction is
fetched from on-chip program memory location 0x0000 once
boot loading completes.
REV. D
–6–
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