ADSP-2181
Table I. Interrupt P riority and Interrupt Vector Addresses
Interrupt Vector
P ower -D own
T he ADSP-2181 processor has a low power feature that lets
the processor enter a very low power dormant state through
hardware or software control. Here is a brief list of power-
down features. For detailed information about the power-
down feature, refer to the ADSP-2100 Family User’s Manual,
Third Edition, “System Interface” chapter.
Source of Interrupt
Address (H ex)
Reset (or Power-Up with PUCR = 1) 0000 (Highest Priority)
Power-Down (Nonmaskable)
IRQ2
002C
0004
IRQL1
IRQL0
0008
000C
• Quick recovery from power-down. T he processor begins
executing instructions in as few as 100 CLKIN cycles.
SPORT 0 T ransmit
SPORT 0 Receive
IRQE
BDMA Interrupt
SPORT 1 T ransmit or IRQ1
SPORT 1 Receive or IRQ0
T imer
0010
0014
0018
001C
0020
0024
• Support for an externally generated T T L or CMOS
processor clock. T he external clock can continue running
during power-down without affecting the lowest power
rating and 100 CLKIN cycle recovery.
• Support for crystal operation includes disabling the oscil-
lator to save power (the processor automatically waits 4096
CLKIN cycles for the crystal oscillator to start and stabi-
lize), and letting the oscillator run to allow 100 CLKIN
cycle start up.
0028 (Lowest Priority)
Interrupt routines can either be nested with higher priority
interrupts taking precedence or processed sequentially. Inter-
rupts can be masked or unmasked with the IMASK register.
Individual interrupt requests are logically ANDed with the bits
in IMASK; the highest priority unmasked interrupt is then
selected. T he power-down interrupt is nonmaskable.
• Power-down is initiated by either the power-down pin
(PWD) or the software power-down force bit.
• Interrupt support allows an unlimited number of instruc-
tions to be executed before optionally powering down.
T he power-down interrupt also can be used as a non-
maskable, edge-sensitive interrupt.
T he ADSP-2181 masks all interrupts for one instruction cycle
following the execution of an instruction that modifies the
IMASK register. T his does not affect serial port autobuffering
or DMA transfers.
• Context clear/save control allows the processor to con-
tinue where it left off or start with a clean context when
leaving the power-down state.
T he interrupt control register, ICNT L, controls interrupt nest-
ing and defines the IRQ0, IRQ1 and IRQ2 external interrupts to
be either edge- or level-sensitive. T he IRQE pin is an external
edge-sensitive interrupt and can be forced and cleared. T he
IRQL0 and IRQL1 pins are external level-sensitive interrupts.
• T he RESET pin also can be used to terminate power-
down.
• Power-down acknowledge pin indicates when the proces-
sor has entered power-down.
T he IFC register is a write-only register used to force and clear
interrupts.
Idle
When the ADSP-2181 is in the Idle Mode, the processor
waits indefinitely in a low power state until an interrupt
occurs. When an unmasked interrupt occurs, it is serviced;
execution then continues with the instruction following the
IDLE instruction.
On-chip stacks preserve the processor status and are automati-
cally maintained during interrupt handling. The stacks are twelve
levels deep to allow interrupt, loop and subroutine nesting.
T he following instructions allow global enable or disable servic-
ing of the interrupts (including power down), regardless of the
state of IMASK. Disabling the interrupts does not affect serial
port autobuffering or DMA.
Slow Idle
T he IDLE instruction is enhanced on the ADSP-2181 to let
the processor’s internal clock signal be slowed, further
reducing power consumption. T he reduced clock fre-
quency, a programmable fraction of the normal clock rate,
is specified by a selectable divisor given in the IDLE in-
struction. T he format of the instruction is
ENA INTS;
DIS INTS;
When the processor is reset, interrupt servicing is enabled.
LO W P O WER O P ERATIO N
IDLE (n);
T he ADSP-2181 has three low power modes that significantly
reduce the power dissipation when the device operates under
standby conditions. T hese modes are:
where n = 16, 32, 64 or 128. T his instruction keeps the
processor fully functional, but operating at the slower clock
rate. While it is in this state, the processor’s other internal
clock signals, such as SCLK, CLKOUT and timer clock,
are reduced by the same ratio. T he default form of the
instruction, when no clock divisor is given, is the standard
IDLE instruction.
• Power-Down
• Idle
• Slow Idle
T he CLKOUT pin may also be disabled to reduce external
power dissipation.
REV. D
–5–
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