Datasheet > 微控制器和处理器 > 数字信号处理器> ADSP-2181KST-115

ADSP-2181KST-115

更新时间： 2024-01-30 03:47:42

品牌	Logo	应用领域
亚德诺 - ADI		微控制器和处理器外围集成电路数字信号处理器装置电脑时钟
页数	文件大小	规格书
32页	293K
描述
DSP Microcomputer

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技术参数
数据手册

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ADSP-2181KST-115 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	TQFP-128
针数：	128	Reach Compliance Code：	not_compliant
ECCN代码：	3A991.A.2	HTS代码：	8542.31.00.01
风险等级：	5.83	其他特性：	33 MIPS SUSTAINED; SINGLE CYCLE INSTRUCTION EXECUTION
地址总线宽度：	14	桶式移位器：	YES
位大小：	16	边界扫描：	NO
最大时钟频率：	14.4 MHz	外部数据总线宽度：	24
格式：	FIXED POINT	集成缓存：	NO
内部总线架构：	MULTIPLE	JESD-30 代码：	R-PQFP-G128
JESD-609代码：	e0	长度：	20 mm
低功率模式：	YES	湿度敏感等级：	3
DMA 通道数量：	2	外部中断装置数量：	4
串行 I/O 数：	2	端子数量：	128
计时器数量：	1	片上数据RAM宽度：	16
片上程序ROM宽度：		最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	LFQFP	封装等效代码：	QFP128,.63X.87,20
封装形状：	RECTANGULAR	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：	240	电源：	5 V
认证状态：	Not Qualified	RAM（字数）：	8192
座面最大高度：	1.6 mm	子类别：	Digital Signal Processors
最大压摆率：	100 mA	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：	1

ADSP-2181KST-115 数据手册

ADSP-2181

ADSP-2181 can fetch an operand from program memory and

the next instruction in the same cycle.

T he ADSP-2181 provides up to 13 general-purpose flag pins.

T he data input and output pins on SPORT 1 can be alternatively

configured as an input flag and an output flag. In addition, there

are eight flags that are programmable as inputs or outputs and

three flags that are always outputs.

In addition to the address and data bus for external memory

connection, the ADSP-2181 has a 16-bit Internal DMA port

(IDMA port) for connection to external systems. T he IDMA

port is made up of 16 data/address pins and five control pins.

T he IDMA port provides transparent, direct access to the DSPs

on-chip program and data RAM.

A programmable interval timer generates periodic interrupts. A

16-bit count register (T COUNT ) is decremented every n pro-

cessor cycles, where n is a scaling value stored in an 8-bit regis-

ter (T SCALE). When the value of the count register reaches

zero, an interrupt is generated and the count register is reloaded

from a 16-bit period register (T PERIOD).

An interface to low cost byte-wide memory is provided by the

Byte DMA port (BDMA port). T he BDMA port is bidirectional

and can directly address up to four megabytes of external RAM

or ROM for off-chip storage of program overlays or data tables.

Ser ial P or ts

T he ADSP-2181 incorporates two complete synchronous serial

ports (SPORT 0 and SPORT 1) for serial communications and

multiprocessor communication.

The byte memory and I/O memory space interface supports slow

memories and I/O memory-mapped peripherals with program-

mable wait state generation. External devices can gain control of

external buses with bus request/grant signals (BR, BGH and BG).

One execution mode (Go Mode) allows the ADSP-2181 to con-

tinue running from on-chip memory. Normal execution mode

requires the processor to halt while buses are granted.

Here is a brief list of the capabilities of the ADSP-2181 SPORTs.

Refer to the ADSP-2100 Family User’s Manual, Third Edition for

further details.

• SPORT s are bidirectional and have a separate, double-

buffered transmit and receive section.

T he ADSP-2181 can respond to 13 possible interrupts, eleven

of which are accessible at any given time. T here can be up to six

external interrupts (one edge-sensitive, two level-sensitive and

three configurable) and seven internal interrupts generated by

the timer, the serial ports (SPORT s), the Byte DMA port and

the power-down circuitry. T here is also a master RESET signal.

• SPORT s can use an external serial clock or generate their

own serial clock internally.

• SPORT s have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of

two pulsewidths and timings.

The two serial ports provide a complete synchronous serial inter-

face with optional companding in hardware and a wide variety of

framed or frameless data transmit and receive modes of operation.

Each port can generate an internal programmable serial clock or

accept an external serial clock.

21xx CORE

ADSP-2181 INTEGRATION

POWER-

DOWN

CONTROL

LOGIC

INSTRUCTION

PROGRAM

SRAM

16K

DATA

SRAM

16K

BYTE

DMA

CONTROLLER

PROGRAMMABLE

I/O

DATA

ADDRESS

GENERATOR

DATA

ADDRESS

GENERATOR

PROGRAM

SEQUENCER

FLAGS

PMA BUS

DMA BUS

PMA BUS

MUX

DMA BUS

EXTERNAL

ADDRESS

BUS

PMD BUS

DMD BUS

PMD BUS

EXTERNAL

DATA

BUS

EXCHANGE

MUX

DMD

BUS

INPUT REGS

SHIFTER

COMPANDING

CIRCUITRY

INTERNAL

DMA

PORT

ALU

MAC

TIMER

TRANSMIT REG

OUTPUT REGS

RECEIVE REG

SERIAL

PORT 0

SERIAL

PORT 0

INTERRUPTS

R BUS

Figure 1. ADSP-2181 Block Diagram

–3–

REV. D

1 234 5 6 7...32

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与ADSP-2181KST-115相关器件

型号	品牌	描述	获取价格	数据表
ADSP-2181KST-133	ADI	DSP Microcomputer	获取价格
ADSP-2181KST-160	ADI	DSP Microcomputer	获取价格
ADSP-2181KSTZ-115	ADI	IC 24-BIT, 14.4 MHz, OTHER DSP, PQFP128, METRIC, PLASTIC, TQFP-128, Digital Signal Process	获取价格
ADSP-2181KSZ-133	ADI	DSP Microcomputer	获取价格
ADSP-2181KSZ-160	ADI	DSP Microcomputer	获取价格
ADSP2183	ADI	DSP Microcomputer	获取价格

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