Datasheet > 微控制器和处理器 > 数字信号处理器> ADSP-21369KBPZ-3A

ADSP-21369KBPZ-3A

更新时间： 2024-01-05 23:39:42

品牌	Logo	应用领域
亚德诺 - ADI		微控制器和处理器外围集成电路数字信号处理器 PC 时钟
页数	文件大小	规格书
60页	1493K
描述
SHARC Processors

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ADSP-21369KBPZ-3A 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	BGA
包装说明：	LBGA, BGA256,20X20,50	针数：	256
Reach Compliance Code：	compliant	ECCN代码：	3A991.A.2
HTS代码：	8542.31.00.01	风险等级：	1.87
Samacsys Confidence：	4	Samacsys Status：	Released
2D Presentation：	https://componentsearchengine.com/2D/0T/154087.1.2.png	Schematic Symbol：	https://componentsearchengine.com/symbol.php?partID=154087
PCB Footprint：	https://componentsearchengine.com/footprint.php?partID=154087	3D View：	https://componentsearchengine.com/viewer/3D.php?partID=154087
Samacsys PartID：	154087	Samacsys Image：	https://componentsearchengine.com/Images/9/ADSP-21369KBPZ-3A.jpg
Samacsys Thumbnail Image：	https://componentsearchengine.com/Thumbnails/1/ADSP-21369KBPZ-3A.jpg	Samacsys Pin Count：	256
Samacsys Part Category：	Integrated Circuit	Samacsys Package Category：	BGA
Samacsys Footprint Name：	BP-256	Samacsys Released Date：	2015-11-26 09:35:24
Is Samacsys：	N	其他特性：	ALSO REQUIRES 3.3V SUPPLY
地址总线宽度：	24	桶式移位器：	YES
位大小：	32	边界扫描：	YES
最大时钟频率：	66.67 MHz	外部数据总线宽度：	32
格式：	FLOATING POINT	内部总线架构：	MULTIPLE
JESD-30 代码：	S-PBGA-B256	JESD-609代码：	e1
长度：	27 mm	低功率模式：	NO
湿度敏感等级：	3	端子数量：	256
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA256,20X20,50	封装形状：	SQUARE
封装形式：	GRID ARRAY, LOW PROFILE	峰值回流温度（摄氏度）：	260
电源：	1.2,3.3 V	认证状态：	Not Qualified
RAM（字数）：	65536	座面最大高度：	1.7 mm
子类别：	Digital Signal Processors	最大供电电压：	1.35 V
最小供电电压：	1.25 V	标称供电电压：	1.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：	BALL	端子节距：	1.27 mm
端子位置：	BOTTOM	处于峰值回流温度下的最长时间：	30
宽度：	27 mm	uPs/uCs/外围集成电路类型：	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches：	1

ADSP-21369KBPZ-3A 数据手册

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ADSP-21367/ADSP-21368/ADSP-21369

processor. The memory architecture, in combination with its

separate on-chip buses, allows two data transfers from the core

and one from the I/O processor, in a single cycle.

Table 3. Internal Memory Space ¹

IOP Registers 0x0000 0000–0x0003 FFFF

Extended Precision Normal or

Long Word (64 Bits)

Instruction Word (48 Bits)

Normal Word (32 Bits)

Short Word (16 Bits)

Block 0 ROM (Reserved)

0x0004 0000–0x0004 BFFF

0x0008 0000–0x0008 FFFF

0x0008 0000–0x0009 7FFF

0x0010 0000–0x0012 FFFF

Reserved

0x0004 F000–0x0004 FFFF

0x0009 4000–0x0009 FFFF

0x0009 E000–0x0009 FFFF

0x0013 C000–0x0013 FFFF

Block 0 SRAM

0x0004 C000–0x0004 EFFF

0x0009 0000–0x0009 3FFF

0x0009 8000–0x0009 DFFF

0x0013 0000–0x0013 BFFF

Block 1 ROM (Reserved)

0x0005 0000–0x0005 BFFF

0x000A 0000–0x000A FFFF

0x000A 0000–0x000B 7FFF

0x0014 0000–0x0016 FFFF

Reserved

0x0005 F000–0x0005 FFFF

0x000B 4000–0x000B FFFF

0x000B E000–0x000B FFFF

0x0017 C000–0x0017 FFFF

Block 1 SRAM

0x0005 C000–0x0005 EFFF

0x000B 0000–0x000B 3FFF

0x000B 8000–0x000B DFFF

0x0017 0000–0x0017 BFFF

Block 2 SRAM

0x0006 0000–0x0006 0FFF

0x000C 0000–0x000C 1554

0x000C 0000–0x000C 1FFF

0x0018 0000–0x0018 3FFF

Reserved

0x0006 1000– 0x0006 FFFF

0x000C 1555–0x000C 3FFF

0x000C 2000–0x000D FFFF

0x0018 4000–0x001B FFFF

Block 3 SRAM

0x0007 0000–0x0007 0FFF

0x000E 0000–0x000E 1554

0x000E 0000–0x000E 1FFF

0x001C 0000–0x001C 3FFF

Reserved

0x0007 1000–0x0007 FFFF

0x000E 1555–0x000F FFFF

0x000E 2000–0x000F FFFF

0x001C 4000–0x001F FFFF

¹The ADSP-21368 and ADSP-21369 processors include a customer-definable ROM block. Please contact your Analog Devices sales representative for additional details.

The SRAM can be configured as a maximum of 64k words of

32-bit data, 128k words of 16-bit data, 42k words of 48-bit

instructions (or 40-bit data), or combinations of different word

sizes up to two megabits. All of the memory can be accessed as

16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point

storage format is supported that effectively doubles the amount

of data that can be stored on-chip. Conversion between the

32-bit floating-point and 16-bit floating-point formats is per-

formed in a single instruction. While each memory block can

store combinations of code and data, accesses are most efficient

when one block stores data using the DM bus for transfers, and

the other block stores instructions and data using the PM bus

for transfers.

On-Chip Memory Bandwidth

The internal memory architecture allows programs to have four

accesses at the same time to any of the four blocks (assuming

there are no block conflicts). The total bandwidth is realized

using the DMD and PMD buses (2x64-bits, core CLK) and the

IOD0/1 buses (2x32-bit, PCLK).

ROM-Based Security

The ADSP-21367/ADSP-21368/ADSP-21369 have a ROM secu-

rity feature that provides hardware support for securing user

software code by preventing unauthorized reading from the

internal code when enabled. When using this feature, the pro-

cessor does not boot-load any external code, executing

exclusively from internal ROM. Additionally, the processor is

not freely accessible via the JTAG port. Instead, a unique 64-bit

key, which must be scanned in through the JTAG or test access

port will be assigned to each customer. The device will ignore a

wrong key. Emulation features and external boot modes are

only available after the correct key is scanned.

Using the DM bus and PM buses, with one bus dedicated to

each memory block, assures single-cycle execution with two

data transfers. In this case, the instruction must be available in

the cache.

Rev. E

| Page 6 of 60 | July 2009

1...3 4 567 8 9...60

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与ADSP-21369KBPZ-3A相关器件

型号	品牌	描述	获取价格	数据表
ADSP-21369KBPZ-ENG	ADI	IC 32-BIT, 66.66 MHz, OTHER DSP, PBGA256, LEAD FREE, MO-192-BAL-2, SBGA-256, Digital Signa	获取价格
ADSP-21369KBPZ-X	ADI	IC 32-BIT, 55.55 MHz, OTHER DSP, PBGA256, LEAD FREE, MO-192BAL-2, SBGA-256, Digital Signal	获取价格
ADSP-21369KSWZ-1A	ADI	SHARC Processors	获取价格
ADSP-21369KSWZ-2A	ADI	SHARC Processors	获取价格
ADSP-21369KSWZ-4A	ADI	SHARC Processors	获取价格
ADSP-21369KSWZ-5A	ADI	SHARC Processors	获取价格

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