ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
pins, one device select pin, and one clock pin. It is a full-duplex
synchronous serial interface, supporting both master and slave
modes and can operate at a maximum baud rate of 41.67 MHz.
TO PROCESSOR BUSES AND
SYSTEM MEMORY
IO DATA
BUS (32)
IO ADDRESS
BUS (18)
The SPI port can operate in a multimaster environment by
interfacing with up to four other SPI-compatible devices, either
acting as a master or slave device. The ADSP-2136x SPI-com-
patible peripheral implementation also features programmable
baud rate, clock phase, and polarities. The SPI-compatible port
uses open drain drivers to support a multimaster configuration
and to avoid data contention.
GPIO FLAGS/IRQ/TIMEXP
4
DMA CONTROLLER
25 CHANNELS
3
CONTROL/GPIO
16
ADDRESS/DATA BUS/ GPIO
PARALLEL PORT
S/PDIF-Compatible Digital Audio Receiver/Transmitter
and Synchronous/Asynchronous Sample Rate Converter
PWM (16)
SPI PORT (1)
The S/PDIF transmitter has no separate DMA channels. It
receives audio data in serial format and converts it into a
biphase encoded signal. The serial data input to the transmitter
can be formatted as left-justified, I2S, or right-justified with
word widths of 16, 18, 20, or 24 bits.
4
4
SPI PORT (1)
SERIAL PORTS (6)
The serial data, clock, and frame sync inputs to the S/PDIF
transmitter are routed through the signal routing unit (SRU).
They can come from a variety of sources such as the SPORTs,
external pins, the precision clock generators (PCGs), or the
sample rate converters (SRC) and are controlled by the SRU
control registers.
INPUT
DATA PORTS (8)
20
DTCP CIPHER
S/PDIF (Rx/Tx)
The sample rate converter (SRC) contains four SRC blocks and
is the same core as that used in the AD1896 192 kHz stereo
asynchronous sample rate converter and provides up to 140 dB
SNR (see Table 2 on Page 4 for details). The SRC block is used
to perform synchronous or asynchronous sample rate conver-
sion across independent stereo channels, without using internal
processor resources. The four SRC blocks can also be config-
ured to operate together to convert multichannel audio data
without phase mismatches. Finally, the SRC is used to clean up
audio data from jittery clock sources such as the S/PDIF
receiver. The S/PDIF and SRC are not available on the
ADSP-21363 models.
SRC (8 CHANNELS)
PRECISION CLOCK
GENERATORS (2)
3
TIMERS (3)
DIGITAL AUDIO INTERFACE
I/O PROCESSOR
Figure 3. ADSP-2136x I/O Processor and
Peripherals Block Diagram
Digital Transmission Content Protection
The DTCP specification defines a cryptographic protocol for
protecting audio entertainment content from illegal copying,
intercepting, and tampering as it traverses high performance
digital buses, such as the IEEE 1394 standard. Only legitimate
entertainment content delivered to a source device via another
approved copy protection system (such as the DVD content
scrambling system) will be protected by this copy protection
system. This feature is available on the ADSP-21362 and
ADSP-21365 processors only. Licensing through DTLA is
required for these products. Visit www.dtcp.com for more
information.
Parallel Port
The parallel port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15–0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8-bit or
16-bit, the maximum data transfer rate is 55 Mbps.
DMA transfers are used to move data to and from internal
memory. Access to the core is also facilitated through the paral-
lel port register read/write functions. The RD, WR, and ALE
(address latch enable) pins are the control pins for the
parallel port.
Pulse-Width Modulation
Serial Peripheral (Compatible) Interface
The PWM module is a flexible, programmable, PWM waveform
generator that can be programmed to generate the required
switching patterns for various applications related to motor and
engine control or audio power control. The PWM generator can
generate either center-aligned or edge-aligned PWM wave-
forms. In addition, it can generate complementary signals on
The processors contain two serial peripheral interface ports
(SPIs). The SPI is an industry-standard synchronous serial link,
enabling the ADSP-2136x SPI-compatible port to communicate
with other SPI-compatible devices. The SPI consists of two data
Rev. C
|
Page 8 of 56
|
September 2007
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