ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366
Harvard architecture, allow unconstrained data flow between
computation units and internal memory. The registers in PEX
are referred to as R0–R15 and in PEY as S0–S15.
The SRAM can be configured as a maximum of 96K words of
32-bit data, 192K words of 16-bit data, 64K words of 48-bit
instructions (or 40-bit data), or combinations of different word
sizes up to three megabits. All of the memory can be accessed as
16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit floating-point
storage format is supported that effectively doubles the amount
of data that may be stored on-chip. Conversion between the 32-
bit floating-point and 16-bit floating-point formats is per-
formed in a single instruction. While each memory block can
store combinations of code and data, accesses are most efficient
when one block stores data using the DM bus for transfers, and
the other block stores instructions and data using the PM bus
for transfers.
Single-Cycle Fetch of Instruction and Four Operands
The ADSP-2136x features an enhanced Harvard architecture in
which the data memory (DM) bus transfers data and the pro-
gram memory (PM) bus transfers both instructions and data
(see Figure 1 on Page 1). With the processor’s separate program
and data memory buses and on-chip instruction cache, the pro-
cessor can simultaneously fetch four operands (two over each
data bus) and one instruction (from the cache), all in a
single cycle.
Using the DM bus and PM buses, with one bus dedicated to
each memory block, assures single-cycle execution with two
data transfers. In this case, the instruction must be available in
the cache.
Instruction Cache
The ADSP-2136x includes an on-chip instruction cache that
enables three-bus operation for fetching an instruction and four
data values. The cache is selective—only the instructions whose
fetches conflict with PM bus data accesses are cached. This
cache allows full-speed execution of core, looped operations
such as digital filter multiply-accumulates, and FFT butterfly
processing.
DMA Controller
The ADSP-2136x’s on-chip DMA controllers allow data trans-
fers without processor intervention. The DMA controller
operates independently and invisibly to the processor core,
allowing DMA operations to occur while the core is simulta-
neously executing its program instructions. DMA transfers can
occur between the processor’s internal memory and its serial
ports, the SPI-compatible (serial peripheral interface) ports, the
IDP (input data port), the parallel data acquisition port (PDAP),
or the parallel port. Twenty-five channels of DMA are available
on the processors—two for the SPI interface, 12 via the serial
ports, eight via the input data port, two for DTCP (or memory-
to-memory data transfer when DTCP is not used), and one via
the processor’s parallel port. Programs can be downloaded to
the processors using DMA transfers. Other DMA features
include interrupt generation upon completion of DMA trans-
fers, and DMA chaining for automatic linked DMA transfers.
Data Address Generators with Zero-Overhead Hardware
Circular Buffer Support
The ADSP-2136x’s two data address generators (DAGs) are
used for indirect addressing and implementing circular data
buffers in hardware. Circular buffers allow efficient program-
ming of delay lines and other data structures required in digital
signal processing, and are commonly used in digital filters and
Fourier transforms. The two DAGs contain sufficient registers
to allow the creation of up to 32 circular buffers (16 primary
register sets, 16 secondary). The DAGs automatically handle
address pointer wraparound, reduce overhead, increase perfor-
mance, and simplify implementation. Circular buffers can start
and end at any memory location.
Digital Audio Interface (DAI)
Flexible Instruction Set
The digital audio interface (DAI) provides the ability to connect
various peripherals to any of the DSP’s DAI pins (DAI_P20–1).
The 48-bit instruction word accommodates a variety of parallel
operations, for concise programming. For example, the
ADSP-2136x can conditionally execute a multiply, an add, and a
subtract in both processing elements while branching and fetch-
ing up to four 32-bit values from memory—all in a single
instruction.
Programs make these connections using the signal routing unit
(SRU, shown in Figure 3).
The SRU is a matrix routing unit (or group of multiplexers) that
enables the peripherals provided by the DAI to be intercon-
nected under software control. This allows easy use of the
DAI- associated peripherals for a much wider variety of applica-
tions by using a larger set of algorithms than is possible with
nonconfigurable signal paths.
MEMORY AND I/O INTERFACE FEATURES
The ADSP-2136x adds the following architectural features to
the SIMD SHARC family core.
The DAI also includes six serial ports, an S/PDIF receiver/trans-
mitter, a DTCP cipher, a precision clock generator (PCG), eight
channels of asynchronous sample rate converters, an input data
port (IDP), an SPI port, six flag outputs and six flag inputs, and
three timers. The IDP provides an additional input path to the
ADSP-2136x core, configurable as either eight channels of I2S
serial data or as seven channels plus a single 20-bit wide syn-
chronous parallel data acquisition port. Each data channel has
its own DMA channel that is independent from the processor’s
serial ports.
On-Chip Memory
The ADSP-2136x contains three megabits of internal SRAM
and four megabits of internal ROM. Each block can be config-
ured for different combinations of code and data storage (see
Table 3). Each memory block supports single-cycle, indepen-
dent accesses by the core processor and I/O processor. The
processor’s memory architecture, in combination with its sepa-
rate on-chip buses, allows two data transfers from the core and
one from the I/O processor, in a single cycle.
Rev. C
|
Page 6 of 56
|
September 2007
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