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ADSP-21366SKBCZENG

更新时间： 2024-02-25 04:58:03
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
54页 523K
描述
SHARC Processor

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ADSP-21366SKBCZENG 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LEAD FREE, MS-026BFB-HD, HSLQFP-144针数：144
Reach Compliance Code：compliantECCN代码：3A991.A.2
HTS代码：8542.31.00.01风险等级：5.84
其他特性：ALSO REQUIRES 3.3V SUPPLY地址总线宽度：16
桶式移位器：YES边界扫描：YES
最大时钟频率：55.55 MHz外部数据总线宽度：16
格式：FLOATING POINT内部总线架构：MULTIPLE
JESD-30 代码：S-PQFP-G144长度：20 mm
低功率模式：NO端子数量：144
最高工作温度：70 °C最低工作温度：
封装主体材料：PLASTIC/EPOXY封装代码：HLFQFP
封装形状：SQUARE封装形式：FLATPACK, HEAT SINK/SLUG, LOW PROFILE, FINE PITCH
峰值回流温度（摄氏度）：NOT SPECIFIED认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压：1.26 V
最小供电电压：1.14 V标称供电电压：1.2 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：20 mm
uPs/uCs/外围集成电路类型：DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches：1

ADSP-21366SKBCZENG 数据手册

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ADSP-21365/6  
Preliminary Technical Data  
Note that the analog supply (AVDD) powers the ADSP-21365/6’s  
clock generator PLL. To produce a stable clock, programs  
should provide an external circuit to filter the power input to  
the AVDD pin. Place the filter as close as possible to the pin. For  
an example circuit, see Figure 4. To prevent noise coupling, use  
a wide trace for the analog ground (AVSS) signal and install a  
decoupling capacitor as close as possible to the pin. Note that  
the AVSS and AVDD pins specified in Figure 4 are inputs to the  
processor and not the analog ground plane on the board. For  
more information, see Electrical Characteristics on page 15.  
Timers  
The ADSP-21365/6 has a total of four timers: a core timer that  
can generate periodic software interrupts and three general pur-  
pose timers that can generate periodic interrupts and be  
independently set to operate in one of three modes:  
• Pulse Waveform Generation mode  
• Pulse Width Count /Capture mode  
• External Event Watchdog mode  
The core timer can be configured to use FLAG3 as a Timer  
Expired signal, and each general purpose timer has one bidirec-  
tional pin and four registers that implement its mode of  
operation: a 6-bit configuration register, a 32-bit count register,  
a 32-bit period register, and a 32-bit pulse width register. A sin-  
gle control and status register enables or disables all three  
general purpose timers independently.  
10⍀  
VDDINT  
AVDD  
0.1␮F  
0.01␮F  
AVSS  
ROM Based Security  
Figure 4. Analog Power (AVDD) Filter Circuit  
The ADSP-21365/6 has a ROM security feature that provides  
hardware support for securing user software code by preventing  
unauthorized reading from the internal code when enabled.  
When using this feature, the processor does not boot-load any  
external code, executing exclusively from internal SRAM/ROM.  
Additionally, the processor is not freely accessible via the JTAG  
port. Instead, a unique 64-bit key, which must be scanned in  
through the JTAG or Test Access Port will be assigned to each  
customer. The device will ignore a wrong key. Emulation fea-  
tures and external boot modes are only available after the  
correct key is scanned.  
Target Board JTAG Emulator Connector  
Analog Devices DSP Tools product line of JTAG emulators uses  
the IEEE 1149.1 JTAG test access port of the ADSP-21365/6  
processor to monitor and control the target board processor  
during emulation. Analog Devices DSP Tools product line of  
JTAG emulators provides emulation at full processor speed,  
allowing inspection and modification of memory, registers, and  
processor stacks. The processor's JTAG interface ensures that  
the emulator will not affect target system loading or timing.  
For complete information on Analog Devices’ SHARC DSP  
Tools product line of JTAG emulator operation, see the appro-  
priate “Emulator Hardware User's Guide”.  
Program Booting  
The internal memory of the ADSP-21365/6 boots at system  
power-up from an 8-bit EPROM via the parallel port, an SPI  
master, an SPI slave or an internal boot. Booting is determined  
by the Boot Configuration (BOOTCFG1–0) pins (see Table 6 on  
page 14). Selection of the boot source is controlled via the SPI as  
either a master or slave device, or it can immediately begin exe-  
cuting from ROM.  
DEVELOPMENT TOOLS  
The ADSP-21365/6 is supported with a complete set of  
CROSSCORE® software and hardware development tools,  
including Analog Devices emulators and VisualDSP++® devel-  
opment environment. The same emulator hardware that  
supports other SHARC processors also fully emulates the  
ADSP-21365/6.  
Phase-Locked Loop  
The VisualDSP++ project management environment lets pro-  
grammers develop and debug an application. This environment  
includes an easy to use assembler (which is based on an alge-  
braic syntax), an archiver (librarian/library builder), a linker, a  
loader, a cycle-accurate instruction-level simulator, a C/C++  
compiler, and a C/C++ runtime library that includes DSP and  
mathematical functions. A key point for these tools is C/C++  
code efficiency. The compiler has been developed for efficient  
translation of C/C++ code to DSP assembly. The SHARC has  
architectural features that improve the efficiency of compiled  
C/C++ code.  
The ADSP-21365/6 uses an on-chip Phase-Locked Loop (PLL)  
to generate the internal clock for the core. On power up, the  
CLKCFG1–0 pins are used to select ratios of 32:1, 16:1, and 6:1  
(see Table 7 on page 14). After booting, numerous other ratios  
can be selected via software control.  
The ratios are made up of software configurable numerator val-  
ues from 1 to 64 and software configurable divisor values of 1, 2,  
4, and 8.  
Power Supplies  
The ADSP-21365/6 has separate power supply connections for  
the internal (VDDINT), external (VDDEXT), and analog  
(AVDD/AVSS) power supplies. The internal and analog supplies  
must meet the 1.2V requirement. The external supply must  
meet the 3.3V requirement. All external supply pins must be  
connected to the same power supply.  
The VisualDSP++ debugger has a number of important fea-  
tures. Data visualization is enhanced by a plotting package that  
offers a significant level of flexibility. This graphical representa-  
tion of user data enables the programmer to quickly determine  
the performance of an algorithm. As algorithms grow in com-  
plexity, this capability can have increasing significance on the  
Rev. PrA  
|
Page 8 of 54  
|
September 2004  
1...567891011...54

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