ADSP-21261
INTERNAL MEMORY
SPACE
LONG WORD
ADDRESSING
NORMAL WORD
ADDRESSING
SHORT WORD
ADDRESSING
IOP REGISTERS
IOP REGISTERS
IOP REGISTERS
0x0000 0000–0x0003 FFFF
0x0000 0000–0x0003 FFFF
0x0000 0000–0x0003 FFFF
BLOCK 0 SRAM (0.5M BIT)
0x0004 0000–0x0004 1FFF
BLOCK 0 SRAM (0.5M BIT)
0x0008 0000–0x0008 3FFF
BLOCK 0 SRAM (0.5M BIT)
0x0010 0000–0x0010 7FFF
RESERVED
RESERVED
RESERVED
0x0004 2000–0x0005 7FFF
0x0008 4000 - 0x000A FFFF
0x0010 8000–0x0015 FFFF
2
BLOCK 0 ROM (1.5M BIT)
0x0005 8000–0x0002 FFFF
BLOCK 0 ROM (1.5M BIT)
0x0016 0000–0x0017 7FFF
BLOCK 0 ROM (1.5M BIT)
0x000B 0000–0x000B BFFF
RESERVED
RESERVED
RESERVED
0x0005 3000–0x0005 FFFF
0x000B C000–0x000B FFFF
0x0017 8FFF–0x0017 FFFF
BLOCK 1 SRAM (0.5M BIT)
0x0006 0000–0x0006 1FFF
BLOCK 1 SRAM (0.5M BIT)
0x000C 0000–0x000C 3FFF
BLOCK 1 SRAM (0.5M BIT)
0x0018 0000–0x0018 7FFF
RESERVED
RESERVED
RESERVED
0x0006 2000–0x0007 7FFF
0x000C 4000–0x000E FFFF
0x0018 8000–0x001D FFFF
3
BLOCK 1 ROM (1.5M BIT)
0x0007 8000–0x0007 DFFF
BLOCK 1 ROM (1.5M BIT)
0x001E 0000–0x001F 7FFF
BLOCK 1 ROM (1.5M BIT)
0x000F 0000–0x000F BFFF
RESERVED
0x0007 E000–0x0007 FFFF
RESERVED
0x000F C000–0x000F FFFF
RESERVED
0x000
EXTERNAL MEMORY
SPACE
1
EXTERNAL MEMORY IS NOT DIRECTLY
ACCESSIBLE BY THE CORE. DMA MUST BE
USED TO READ OR WRITE TO THIS MEMO RY
US ING THE SP I O R P ARA LL EL POR T.
RESERVED
0x0020 0000–0x00FF FFFF
2
3
BLOCK 0 ROM HAS A 48-BIT ADDRESS RANGE
(0xA0000–0xA7 FFFF).
EXTERNAL DMA
1
ADDRESS SPACE
0x0100 0000–0x02FF FFFF
BLOCK 1 ROM HAS A 48-BIT ADDRESS RANGE
(0xE0000–0xE7 FFFF).
RESERVED
0x0300 0000–0x3FFF FFFF
Figure 3. ADSP-21261 Memory Map
37.5 MHz, clock phases, and polarities. The ADSP-21261 SPI-
compatible port uses open-drain drivers to support a multimas-
ter configuration and to avoid data contention.
Serial Peripheral (Compatible) Interface
Serial peripheral interface is an industry-standard synchronous
serial link, enabling the ADSP-21261 SPI-compatible port to
communicate with other SPI-compatible devices. SPI is an
interface consisting of two data pins, one device select pin, and
one clock pin. It is a full-duplex synchronous serial interface,
supporting both master and slave modes. The SPI port can
operate in a multimaster environment by interfacing with up to
four other SPI-compatible devices, either acting as a master or
slave device. The ADSP-21261 SPI-compatible peripheral
implementation also features programmable baud rates up to
Parallel Port
The parallel port provides interfaces to SRAM and peripheral
devices. The multiplexed address and data pins (AD15–0) can
access 8-bit devices with up to 24 bits of address, or 16-bit
devices with up to 16 bits of address. In either mode, 8- or 16-
bit, the maximum data transfer rate is one-third the core clock
speed. As an example, a clock rate of 200 MHz is equivalent to
66M byte/s, and a clock rate of 150 MHz is equivalent to
50M byte/s.
Rev. 0
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Page 7 of 44 | March 2006