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ADSP-21160NCB-100 PDF预览

ADSP-21160NCB-100

更新时间: 2024-02-27 22:32:46
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器时钟
页数 文件大小 规格书
60页 1205K
描述
SHARC Digital Signal Processor

ADSP-21160NCB-100 技术参数

是否无铅: 含铅是否Rohs认证: 不符合
生命周期:Active零件包装代码:BGA
包装说明:BGA,针数:400
Reach Compliance Code:unknown风险等级:5.74
Is Samacsys:N其他特性:ALSO REQUIRES 3.3V SUPPLY
地址总线宽度:32桶式移位器:YES
边界扫描:YES最大时钟频率:50 MHz
外部数据总线宽度:64格式:FLOATING POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PBGA-B400
JESD-609代码:e0长度:27 mm
低功率模式:NO湿度敏感等级:3
端子数量:400封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装形状:SQUARE
封装形式:GRID ARRAY峰值回流温度(摄氏度):225
认证状态:COMMERCIAL座面最大高度:2.49 mm
最大供电电压:2 V最小供电电压:1.8 V
标称供电电压:1.9 V表面贴装:YES
技术:CMOS端子面层:TIN LEAD SILVER
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:27 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches:1

ADSP-21160NCB-100 数据手册

 浏览型号ADSP-21160NCB-100的Datasheet PDF文件第7页浏览型号ADSP-21160NCB-100的Datasheet PDF文件第8页浏览型号ADSP-21160NCB-100的Datasheet PDF文件第9页浏览型号ADSP-21160NCB-100的Datasheet PDF文件第11页浏览型号ADSP-21160NCB-100的Datasheet PDF文件第12页浏览型号ADSP-21160NCB-100的Datasheet PDF文件第13页 
ADSP-21160M/ADSP-21160N  
located on the web page for the associated EZ-KIT or EZ-  
Extender product. The link is found in the Product Download  
area of the product web page.  
output of one portion of the chain supplying input to the next.  
Signal chains are often used in signal processing applications to  
gather and process data or to apply system controls based on  
analysis of real-time phenomena. For more information about  
this term and related topics, see the “signal chain” entry in the  
Glossary of EE Terms on the Analog Devices website.  
Middleware Packages  
Analog Devices separately offers middleware add-ins such as  
real time operating systems, file systems, USB stacks, and  
TCP/IP stacks. For more information, see the following web  
pages:  
Analog Devices eases signal processing system development by  
providing signal processing components that are designed to  
work together well. A tool for viewing relationships between  
specific applications and related components is available on the  
www.analog.com website.  
www.analog.com/ucos3  
www.analog.com/ucfs  
www.analog.com/ucusbd  
www.analog.com/lwip  
TM  
The Circuits from the Lab site (www.analog.com/signal  
chains) provides:  
• Graphical circuit block diagram presentation of signal  
chains for a variety of circuit types and applications  
Algorithmic Modules  
• Drill down links for components in each chain to selection  
guides and application information  
To speed development, Analog Devices offers add-ins that per-  
form popular audio and video processing algorithms. These are  
available for use with both CrossCore Embedded Studio and  
VisualDSP++. For more information visit www.analog.com and  
search on “Blackfin software modules” or “SHARC software  
modules”.  
• Reference designs applying best practice design techniques  
Designing an Emulator-Compatible DSP Board (Target)  
For embedded system test and debug, Analog Devices provides  
a family of emulators. On each JTAG DSP, Analog Devices sup-  
plies an IEEE 1149.1 JTAG Test Access Port (TAP). In-circuit  
emulation is facilitated by use of this JTAG interface. The emu-  
lator accesses the processor’s internal features via the  
processor’s TAP, allowing the developer to load code, set break-  
points, and view variables, memory, and registers. The  
processor must be halted to send data and commands, but once  
an operation is completed by the emulator, the DSP system is set  
to run at full speed with no impact on system timing. The emu-  
lators require the target board to include a header that supports  
connection of the DSP’s JTAG port to the emulator.  
For details on target board design issues including mechanical  
layout, single processor connections, signal buffering, signal ter-  
mination, and emulator pod logic, see the EE-68: Analog Devices  
JTAG Emulation Technical Reference on the Analog Devices  
website (www.analog.com)—use site search on “EE-68.” This  
document is updated regularly to keep pace with improvements  
to emulator support.  
ADDITIONAL INFORMATION  
This data sheet provides a general overview of the  
ADSP-21160x architecture and functionality. For detailed infor-  
mation on the Blackfin family core architecture and instruction  
set, refer to the ADSP-21160 SHARC DSP Hardware Reference  
and the ADSP-21160 SHARC DSP Instruction Set Reference. For  
detailed information on the development tools for this proces-  
sor, see the VisualDSP++ User’s Guide.  
RELATED SIGNAL CHAINS  
A signal chain is a series of signal conditioning electronic com-  
ponents that receive input (data acquired from sampling either  
real-time phenomena or from stored data) in tandem, with the  
Rev. C  
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Page 10 of 60  
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February 2013  

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ADSP-21160NCB-100 ADI

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