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ADSP-21060LAB-160 PDF预览

ADSP-21060LAB-160

更新时间: 2024-01-18 09:58:32
品牌 Logo 应用领域
亚德诺 - ADI 外围集成电路时钟
页数 文件大小 规格书
47页 364K
描述
ADSP-2106x SHARC DSP Microcomputer Family

ADSP-21060LAB-160 技术参数

Source Url Status Check Date:2013-05-01 14:56:48.174是否无铅: 含铅
是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:PLASTIC, MS-034AAJ-2, BGA-225
针数:225Reach Compliance Code:not_compliant
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.62地址总线宽度:32
桶式移位器:YES位大小:32
边界扫描:YES最大时钟频率:40 MHz
外部数据总线宽度:48格式:FLOATING POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PBGA-B225
JESD-609代码:e0长度:23 mm
低功率模式:YES湿度敏感等级:3
端子数量:225最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:BGA封装等效代码:BGA225,15X15,50
封装形状:SQUARE封装形式:GRID ARRAY
峰值回流温度(摄氏度):225电源:3.3 V
认证状态:Not QualifiedRAM(字数):131072
座面最大高度:2.7 mm子类别:Digital Signal Processors
最大压摆率:600 mA最大供电电压:3.45 V
最小供电电压:3.15 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead/Silver (Sn62Pb36Ag2)
端子形式:BALL端子节距:1.27 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:23 mmuPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHER

ADSP-21060LAB-160 数据手册

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ADSP-21060/ADSP-21060L  
Serial Ports  
Link Ports  
The ADSP-2106x features two synchronous serial ports that  
provide an inexpensive interface to a wide variety of digital and  
mixed-signal peripheral devices. The serial ports can operate at  
the full clock rate of the processor, providing each with a maxi-  
mum data rate of 40 Mbit/s. Independent transmit and receive  
functions provide greater flexibility for serial communications.  
Serial port data can be automatically transferred to and from  
on-chip memory via DMA. Each of the serial ports offers TDM  
multichannel mode.  
The ADSP-2106x features six 4-bit link ports that provide addi-  
tional I/O capabilities. The link ports can be clocked twice per  
cycle, allowing each to transfer eight bits per cycle. Link port  
I/O is especially useful for point-to-point interprocessor commu-  
nication in multiprocessing systems.  
The link ports can operate independently and simultaneously,  
with a maximum data throughput of 240 Mbytes/s. Link port  
data is packed into 32- or 48-bit words, and can be directly read  
by the core processor or DMA-transferred to on-chip memory.  
The serial ports can operate with little-endian or big-endian  
transmission formats, with word lengths selectable from 3 bits to  
32 bits. They offer selectable synchronization and transmit  
modes as well as optional µ-law or A-law companding. Serial  
port clocks and frame syncs can be internally or externally  
generated.  
Each link port has its own double-buffered input and output  
registers. Clock/acknowledge handshaking controls link port  
transfers. Transfers are programmable as either transmit or  
receive.  
Program Booting  
The internal memory of the ADSP-2106x can be booted at  
system power-up from either an 8-bit EPROM, a host proces-  
sor, or through one of the link ports. Selection of the boot  
source is controlled by the BMS (Boot Memory Select),  
EBOOT (EPROM Boot), and LBOOT (Link/Host Boot) pins.  
32-bit and 16-bit host processors can be used for booting.  
Multiprocessing  
The ADSP-2106x offers powerful features tailored to multi-  
processing DSP systems. The unified address space (see  
Figure 4) allows direct interprocessor accesses of each ADSP-  
2106x’s internal memory. Distributed bus arbitration logic is  
included on-chip for simple, glueless connection of systems  
containing up to six ADSP-2106xs and a host processor. Master  
processor changeover incurs only one cycle of overhead. Bus  
arbitration is selectable as either fixed or rotating priority. Bus lock  
allows indivisible read-modify-write sequences for semaphores. A  
vector interrupt is provided for interprocessor commands. Maxi-  
mum throughput for interprocessor data transfer is 240 Mbytes/s  
over the link ports or external port. Broadcast writes allow simulta-  
neous transmission of data to all ADSP-2106xs and can be used  
to implement reflective semaphores.  
REV. D  
–5–  

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