Datasheet > ADSP-21061

ADSP-21061

更新时间： 2024-11-06 22:35:15

品牌	Logo	应用领域
亚德诺 - ADI		/
页数	文件大小	规格书
47页	366K
描述
ADSP-2106x SHARC DSP Microcomputer Family

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中文翻译

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数据手册

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ADSP-21061 数据手册

ADSP-2106x SHARC

DSP Microcomputer Family

ADSP-21061/ADSP-21061L

Pin-Compatible with ADSP-21060 (4 Mbit) and

ADSP-21062 (2 Mbit)

SUMMARY

High Performance Signal Computer for Speech, Sound,

Graphics and Imaging Applications

Super Harvard Architecture Computer (SHARC)—

Four Independent Buses for Dual Data, Instructions,

and I/O

32-Bit IEEE Floating-Point Computation Units—

Multiplier, ALU and Shifter

1 Megabit On-Chip SRAM Memory and Integrated I/O

Peripherals—A Complete System-On-A-Chip

Integrated Multiprocessing Features

Flexible Data Formats and 40-Bit Extended Precision

32-Bit Single-Precision and 40-Bit Extended-Precision

IEEE Floating-Point Data Formats

32-Bit Fixed-Point Data Format, Integer and Fractional,

with 80-Bit Accumulators

Parallel Computations

Single-Cycle Multiply and ALU Operations in Parallel with

Dual Memory Read/Writes and Instruction Fetch

Multiply with Add and Subtract for Accelerated FFT

Butterfly Computation

KEY FEATURES

50 MIPS, 20 ns Instruction Rate, Single-Cycle Instruction

Execution

120 MFLOPS Peak, 80 MFLOPS Sustained Performance

Dual Data Address Generators with Modulo and Bit-

Reverse Addressing

Efficient Program Sequencing with Zero-Overhead

Looping: Single-Cycle Loop Setup

IEEE JTAG Standard 1149.1 Test Access Port and

On-Chip Emulation

1024-Point Complex FFT Benchmark: 0.37 ms (18,221 Cycles)

1 Megabit Configurable On-Chip SRAM

Dual-Ported for Independent Access by Core Processor

and DMA

Configurable as 32K Words Data Memory (32-Bit), 16K

Words Program Memory (48-Bit) or Combinations of

Both Up to 1 Mbit

Off-Chip Memory Interfacing

4-Gigawords Addressable (32-Bit Address)

Programmable Wait State Generation, Page-Mode DRAM

Support

240-Lead MQFP Package

225-Ball Plastic Ball Grid Array (PBGA)

DUAL-PORTED SRAM

CORE PROCESSOR

INSTRUCTION

TIMER

JTAG

TWO INDEPENDENT

CACHE

DUAL-PORTED BLOCKS

32 x 48-BIT

TEST &

EMULATION

PROCESSOR PORT

ADDR DATA

I/O PORT

DATA ADDR

ADDR

DATA

ADDR

DAG1

DAG2

PROGRAM

SEQUENCER

8 x 4 x 32

8 x 4 x 24

EXTERNAL

PORT

IOD

IOA

PM ADDRESS BUS

ADDR BUS

MUX

DM ADDRESS BUS

MULTIPROCESSOR

INTERFACE

PM DATA BUS

DM DATA BUS

BUS

CONNECT

(PX)

DATA BUS

MUX

40/32

HOST PORT

DATA

FILE

DMA

IOP

REGISTERS

(MEMORY MAPPED)

CONTROLLER

16 x 40-BIT

BARREL

SHIFTER

MULTIPLIER

ALU

SERIAL PORTS

(2)

CONTROL,

STATUS &

DATA BUFFERS

I/O PROCESSOR

Figure 1. ADSP-21061/ADSP-21061L Block Diagram

SHARC is a registered trademark of Analog Devices, Inc.

REV. B

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, nor for any infringements of patents or other rights of third parties

which may result from its use. No license is granted by implication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

World Wide Web Site: http://www.analog.com

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与ADSP-21061相关器件

型号	品牌	获取价格	描述	数据表
ADSP-21061_15	ADI	获取价格	Commercial Grade SHARC DSP Microcomputer
ADSP-21061KS-133	ADI	获取价格	ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061KS-160	ADI	获取价格	ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061KS-200	ADI	获取价格	ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061KS-200X	ETC	获取价格	32-Bit Digital Signal Processor
ADSP-21061KSZ-133	ADI	获取价格	Commercial Grade SHARC DSP Microcomputer
ADSP-21061KSZ-160	ADI	获取价格	Commercial Grade SHARC DSP Microcomputer
ADSP-21061KSZ-200	ADI	获取价格	Commercial Grade SHARC DSP Microcomputer
ADSP-21061L	ADI	获取价格	ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061L_15	ADI	获取价格	Commercial Grade SHARC DSP Microcomputer

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