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ADSP-21060LKB-160

更新时间： 2024-11-23 22:07:51
品牌 Logo 应用领域
亚德诺 - ADI 外围集成电路时钟
页数 文件大小 规格书
47页 364K
描述
ADSP-2106x SHARC DSP Microcomputer Family

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ADSP-21060LKB-160 数据手册

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®
ADSP-2106x SHARC  
a
DSP Microcomputer Family  
ADSP-21060/ADSP-21060L  
IEEE JTAG Standard 1149.1 Test Access Port and  
On-Chip Emulation  
SUMMARY  
High Performance Signal Processor for Communica-  
tions, Graphics, and Imaging Applications  
Super Harvard Architecture  
240-Lead Thermally Enhanced MQFP Package  
225 PBGA Package  
32-Bit Single-Precision and 40-Bit Extended-Precision  
IEEE Floating-Point Data Formats or 32-Bit Fixed-  
Point Data Format  
Four Independent Buses for Dual Data Fetch,  
Instruction Fetch, and Nonintrusive I/O  
32-Bit IEEE Floating-Point Computation Units—  
Multiplier, ALU, and Shifter  
Dual-Ported On-Chip SRAM and Integrated I/O  
Peripherals—A Complete System-On-A-Chip  
Integrated Multiprocessing Features  
Parallel Computations  
Single-Cycle Multiply and ALU Operations in Parallel  
with Dual Memory Read/Writes and Instruction Fetch  
Multiply with Add and Subtract for Accelerated FFT  
Butterfly Computation  
KEY FEATURES  
40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction  
Execution  
120 MFLOPS Peak, 80 MFLOPS Sustained Performance  
Dual Data Address Generators with Modulo and Bit-  
Reverse Addressing  
4 Mbit On-Chip SRAM  
Dual-Ported for Independent Access by Core Processor  
and DMA  
Off-Chip Memory Interfacing  
4 Gigawords Addressable  
Programmable Wait State Generation, Page-Mode  
DRAM Support  
Efficient Program Sequencing with Zero-Overhead  
Looping: Single-Cycle Loop Setup  
DUAL-PORTED SRAM  
CORE PROCESSOR  
INSTRUCTION  
CACHE  
32 
؋
 48-BIT  
TIMER  
TWO INDEPENDENT  
JTAG  
TEST &  
EMULATION  
7
DUAL-PORTED BLOCKS  
PROCESSOR PORT  
I/O PORT  
ADDR  
DATA  
DATA  
ADDR  
ADDR  
DATA  
DATA  
ADDR  
DAG1  
8 
؋
 4 
؋
32  
DAG2  
8 
؋
 4 
؋
24  
PROGRAM  
SEQUENCER  
EXTERNAL  
PORT  
IOD  
48  
IOA  
17  
PM ADDRESS BUS  
DM ADDRESS BUS  
24  
32  
32  
48  
ADDR BUS  
MUX  
MULTIPROCESSOR  
INTERFACE  
PM DATA BUS  
48  
BUS  
CONNECT  
(PX)  
DATA BUS  
MUX  
40/32  
DM DATA BUS  
HOST PORT  
4
6
DMA  
CONTROLLER  
DATA  
REGISTER  
FILE  
IOP  
REGISTERS  
(MEMORY MAPPED)  
SERIAL PORTS  
(2)  
16 
؋
 40-BIT  
BARREL  
SHIFTER  
6
MULTIPLIER  
ALU  
CONTROL,  
STATUS &  
DATA BUFFERS  
36  
LINK PORTS  
(6)  
I/O PROCESSOR  
Figure 1. Block Diagram  
SHARC is a registered trademark of Analog Devices, Inc.  
REV. D  
Information furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assumed by Analog Devices for its  
use, nor for any infringements of patents or other rights of third parties  
which may result from its use. No license is granted by implication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781/329-4700  
Fax: 781/326-8703  
World Wide Web Site: http://www.analog.com  
© Analog Devices, Inc., 2000  
1234567...47

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