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ADSP-21061KSZ-160 PDF预览

ADSP-21061KSZ-160

更新时间： 2024-11-24 12:33:19
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器装置时钟
页数 文件大小 规格书
52页 870K
描述
Commercial Grade SHARC DSP Microcomputer

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ADSP-21061KSZ-160 数据手册

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Commercial Grade  
SHARC DSP Microcomputer  
a
ADSP-21061/ADSP-21061L  
Dual data address generators with modulo and bit-reverse  
addressing  
Efficient program sequencing with zero-overhead looping:  
single-cycle loop setup  
IEEE JTAG Standard 1149.1 test access port and on-chip  
emulation  
32-bit single-precision and 40-bit extended-precision IEEE  
floating-point data formats or 32-bit fixed-point data  
format  
240-lead MQFP package, thermally enhanced MQFP, 225-ball  
plastic ball grid array (PBGA)  
Lead (Pb) free packages. For more information, see Ordering  
Guide on Page 52.  
SUMMARY  
High performance signal processor for communications,  
graphics, and imaging applications  
Super Harvard Architecture  
Four independent buses for dual data fetch, instruction  
fetch, and nonintrusive I/O  
32-bit IEEE floating-point computation units—multiplier,  
ALU, and shifter  
Dual-ported on-chip SRAM and integrated I/O peripherals—a  
complete system-on-a-chip  
Integrated multiprocessing features  
KEY FEATURES—PROCESSOR CORE  
50 MIPS, 20 ns instruction rate, single-cycle instruction  
execution  
120 MFLOPS peak, 80 MFLOPS sustained performance  
CORE PROCESSOR  
DUAL-PORTED SRAM  
INSTRUCTION  
TIMER  
JTAG  
TWO INDEPENDENT  
DUAL-PORTED BLOCKS  
7
CACHE  
TEST AND  
EMULATION  
32 ϫ 48-BIT  
PROCESSOR PORT  
ADDR DATA  
ADDR  
I/O PORT  
ADDR  
ADDR  
DATA  
DATA  
DATA  
DAG1  
DAG2  
PROGRAM  
SEQUENCER  
8 ϫ 4 ϫ 32 8 ϫ 4 ϫ 24  
EXTERNAL  
PORT  
IOD  
48  
IOA  
17  
24  
PM ADDRESS BUS  
32  
48  
ADDR BUS  
MUX  
DM ADDRESS BUS  
32  
MULTIPROCESSOR  
INTERFACE  
48  
40/32  
PM DATA BUS  
DM DATA BUS  
BUS  
CONNECT  
(PX)  
DATA BUS  
MUX  
HOST PORT  
S
DATA  
REGISTER  
FILE  
IOP  
4
DMA  
CONTROLLER  
REGISTERS  
(MEMORY  
MAPPED)  
6
6
BARREL  
SHIFTER  
16 ϫ 40-BIT  
MULT  
ALU  
CONTROL,  
STATUS AND  
DATA BUFFERS  
SERIAL PORTS  
(2)  
I/O PROCESSOR  
Figure 1. Functional Block Diagram  
SHARC and the SHARC logo are registered trademarks of Analog Devices, Inc.  
Rev. D Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2013 Analog Devices, Inc. All rights reserved.  
www.analog.com  
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ADSP-21061KSZ-160 替代型号

型号 品牌 替代类型 描述 数据表
ADSP-21060KSZ-160 ADI

类似代替

 SHARC Processor
ADSP-21060KS-160 ADI

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 ADSP-2106x SHARC DSP Microcomputer Family

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ADSP-21061L_15 ADI

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ADSP-21061LAS-160 ADI

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ADSP-21061LAS-176 ADI

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ADSP-21061LASZ-176 ADI

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 		Commercial Grade SHARC DSP Microcomputer
ADSP-21061LKB-160 ADI

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 		ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKB-176 ADI

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 		ADSP-2106x SHARC DSP Microcomputer Family
ADSP-21061LKBZ-160 ADI

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 		Commercial Grade SHARC DSP Microcomputer
ADSP-21061LKS-160 ADI

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 		ADSP-2106x SHARC DSP Microcomputer Family

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