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ADSP-21060KSZ-160 PDF预览

ADSP-21060KSZ-160

更新时间: 2024-02-02 12:15:19
品牌 Logo 应用领域
亚德诺 - ADI 微控制器和处理器外围集成电路数字信号处理器装置时钟
页数 文件大小 规格书
64页 817K
描述
SHARC Processor

ADSP-21060KSZ-160 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:QFP
包装说明:HFQFP,针数:240
Reach Compliance Code:unknown风险等级:5.41
Is Samacsys:N其他特性:40 MIPS; 16/32 BIT PARALLEL HOST INTERFACE PORT; 120 MFLOPS PEAK; 80 MFLOPS SUSTAINED
地址总线宽度:32桶式移位器:YES
边界扫描:YES最大时钟频率:40 MHz
外部数据总线宽度:48格式:FLOATING POINT
内部总线架构:MULTIPLEJESD-30 代码:S-PQFP-G240
JESD-609代码:e3长度:32 mm
低功率模式:YES湿度敏感等级:3
端子数量:240最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:HFQFP封装形状:SQUARE
封装形式:FLATPACK, HEAT SINK/SLUG, FINE PITCH峰值回流温度(摄氏度):260
认证状态:COMMERCIAL座面最大高度:4.1 mm
最大供电电压:5.25 V最小供电电压:4.75 V
标称供电电压:5 V表面贴装:YES
技术:CMOS温度等级:OTHER
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:32 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

ADSP-21060KSZ-160 数据手册

 浏览型号ADSP-21060KSZ-160的Datasheet PDF文件第5页浏览型号ADSP-21060KSZ-160的Datasheet PDF文件第6页浏览型号ADSP-21060KSZ-160的Datasheet PDF文件第7页浏览型号ADSP-21060KSZ-160的Datasheet PDF文件第9页浏览型号ADSP-21060KSZ-160的Datasheet PDF文件第10页浏览型号ADSP-21060KSZ-160的Datasheet PDF文件第11页 
ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC  
the real-time characteristics of the program. Essentially, the  
developer can identify bottlenecks in software quickly and effi-  
ciently. By using the profiler, the programmer can focus on  
those areas in the program that impact performance and take  
corrective action.  
Link Ports  
The ADSP-2106x features six 4-bit link ports that provide addi-  
tional I/O capabilities. The link ports can be clocked twice per  
cycle, allowing each to transfer eight bits of data per cycle. Link-  
port I/O is especially useful for point-to-point interprocessor  
communication in multiprocessing systems.  
Debugging both C/C++ and assembly programs with the  
VisualDSP++ debugger, programmers can:  
The link ports can operate independently and simultaneously,  
with a maximum data throughput of 240M bytes/s. Link port  
data is packed into 32- or 48-bit words, and can be directly read  
by the core processor or DMA-transferred to on-chip memory.  
• View mixed C/C++ and assembly code (interleaved source  
and object information)  
• Insert breakpoints  
Each link port has its own double-buffered input and output  
registers. Clock/acknowledge handshaking controls link port  
transfers. Transfers are programmable as either transmit or  
receive.  
• Set conditional breakpoints on registers, memory, and  
stacks  
• Trace instruction execution  
• Perform linear or statistical profiling of program execution  
• Fill, dump, and graphically plot the contents of memory  
• Perform source level debugging  
Program Booting  
The internal memory of the ADSP-2106x can be booted at sys-  
tem power-up from an 8-bit EPROM, a host processor, or  
through one of the link ports. Selection of the boot source is  
controlled by the BMS (boot memory select), EBOOT (EPROM  
Boot), and LBOOT (link/host boot) pins. 32-bit and 16-bit host  
processors can be used for booting. The processor also sup-  
ports a no-boot mode in which instruction execution is sourced  
from the external memory.  
• Create custom debugger windows  
The VisualDSP++ IDDE lets programmers define and manage  
DSP software development. Its dialog boxes and property pages  
let programmers configure and manage all of the ADSP-2106x  
development tools, including the color syntax highlighting in  
the VisualDSP++ editor. This capability permits:  
DEVELOPMENT TOOLS  
• Control in how the development tools process inputs and  
generate outputs  
The ADSP-2106x is supported by a complete set of  
CROSSCORE®software development tools, including Analog  
Devices emulators and VisualDSP++®development environ-  
ment. The same emulator hardware that supports other SHARC  
processors also fully emulates the ADSP-2106x.  
• Maintenance of a one-to-one correspondence with the  
tools’ command line switches  
The VisualDSP++ kernel (VDK) incorporates scheduling and  
resource management tailored specifically to address the mem-  
ory and timing constraints of DSP programming. These  
capabilities enable engineers to develop code more effectively,  
eliminating the need to start from the very beginning when  
developing new application code. The VDK features include  
threads, critical and unscheduled regions, semaphores, events,  
and device flags. The VDK also supports priority-based, pre-  
emptive, cooperative, and time-sliced scheduling approaches. In  
addition, the VDK was designed to be scalable. If the application  
does not use a specific feature, the support code for that feature  
is excluded from the target system.  
The VisualDSP++ project management environment lets pro-  
grammers develop and debug an application. This environment  
includes an easy to use assembler (which is based on an alge-  
braic syntax), an archiver (librarian/library builder), a linker, a  
loader, a cycle-accurate instruction-level simulator, a C/C++  
compiler, and a C/C++ runtime library that includes DSP and  
mathematical functions. A key point for these tools is C/C++  
code efficiency. The compiler has been developed for efficient  
translation of C/C++ code to DSP assembly. The ADSP-2106x  
SHARC DSP has architectural features that improve the effi-  
ciency of compiled C/C++ code.  
Because the VDK is a library, a developer can decide whether to  
use it or not. The VDK is integrated into the VisualDSP++  
development environment, but can also be used via standard  
command line tools. When the VDK is used, the development  
environment assists the developer with many error-prone tasks  
and assists in managing system resources, automating the gen-  
eration of various VDK-based objects, and visualizing the  
system state, when debugging an application that uses the VDK.  
The VisualDSP++ debugger has a number of important fea-  
tures. Data visualization is enhanced by a plotting package that  
offers a significant level of flexibility. This graphical representa-  
tion of user data enables the programmer to quickly determine  
the performance of an algorithm. As algorithms grow in com-  
plexity, this capability can have increasing significance on the  
designer’s development schedule, increasing productivity. Sta-  
tistical profiling enables the programmer to nonintrusively poll  
the processor as it is running the program. This feature, unique  
to VisualDSP++, enables the software developer to passively  
gather important code execution metrics without interrupting  
Use the expert linker to visually manipulate the placement of  
code and data on the embedded system. View memory utiliza-  
tion in a color-coded graphical form, easily move code and data  
to different areas of the DSP or external memory with a drag of  
the mouse, and examine run-time stack and heap usage. The  
CROSSCORE is a registered trademark of Analog Devices, Inc.  
VisualDSP++ is a registered trademark of Analog Devices, Inc.  
Rev. F  
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Page 8 of 64  
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March 2008  

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