®
ADSP-21060 Industrial SHARC
a
DSP Microcomputer Family
ADSP-21060C/ADSP-21060LC
SUMMARY
Efficient Program Sequencing with Zero-Overhead
Looping: Single-Cycle Loop Setup
High Performance Signal Processor for Communica-
tions, Graphics, and Imaging Applications
Super Harvard Architecture
IEEE JTAG Standard 1149.1 Test Access Port and
On-Chip Emulation
Four Independent Buses for Dual Data Fetch,
Instruction Fetch, and Nonintrusive I/O
32-Bit IEEE Floating-Point Computation Units—
Multiplier, ALU, and Shifter
240-Lead Thermally Enhanced CQFP Package
32-Bit Single-Precision and 40-Bit Extended-Precision
IEEE Floating-Point Data Formats or 32-Bit Fixed-
Point Data Format
Dual-Ported On-Chip SRAM and Integrated I/O
Peripherals—A Complete System-On-A-Chip
Integrated Multiprocessing Features
Industrial Temperature Grade Hermetic Ceramic QFP
Package
Parallel Computations
Single-Cycle Multiply and ALU Operations in Parallel
with Dual Memory Read/Writes and Instruction Fetch
Multiply with Add and Subtract for Accelerated FFT
Butterfly Computation
KEY FEATURES
40 MIPS, 25 ns Instruction Rate, Single-Cycle Instruction
Execution
120 MFLOPS Peak, 80 MFLOPS Sustained Performance
Dual Data Address Generators with Modulo and Bit-
Reverse Addressing
4 Mbit On-Chip SRAM
Dual-Ported for Independent Access by Core Processor
and DMA
Off-Chip Memory Interfacing
4 Gigawords Addressable
Programmable Wait State Generation, Page-Mode
DRAM Support
DUAL-PORTED SRAM
CORE PROCESSOR
TIMER
INSTRUCTION
JTAG
TWO INDEPENDENT
7
CACHE
DUAL-PORTED BLOCKS
32 x 48-BIT
TEST &
EMULATION
PROCESSOR PORT
I/O PORT
ADDR
DATA
DATA
ADDR
DATA
ADDR
ADDR
DATA
DAG1
DAG2
PROGRAM
SEQUENCER
8 x 4 x 32
8 x 4 x 24
EXTERNAL
PORT
IOD
48
IOA
17
24
PM ADDRESS BUS
32
48
ADDR BUS
MUX
32
DM ADDRESS BUS
MULTIPROCESSOR
INTERFACE
PM DATA BUS
DM DATA BUS
48
BUS
DATA BUS
MUX
CONNECT
(PX)
40/32
HOST PORT
4
DMA
DATA
IOP
REGISTERS
CONTROLLER
REGISTER
FILE
6
6
(
MEMORY MAPPED)
SERIAL PORTS
(2)
16 x 40-BIT
BARREL
SHIFTER
ALU
MULTIPLIER
CONTROL,
STATUS &
DATA BUFFERS
36
LINK PORTS
(6)
I/O PROCESSOR
Figure 1. Block Diagram
SHARC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2001