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ADS54T02IZAYR PDF预览

ADS54T02IZAYR

更新时间: 2024-11-29 12:51:43
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德州仪器 - TI /
页数 文件大小 规格书
44页 1282K
描述
Dual Channel 12-Bit 750 Msps Receiver and Feedback IC

ADS54T02IZAYR 数据手册

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ADS54T02  
www.ti.com  
SLAS933 JANUARY 2013  
Dual Channel 12-Bit 750 Msps Receiver and Feedback IC  
Check for Samples: ADS54T02  
1
FEATURES  
Dual Channel  
Performance at fin = 700 MHz IF  
12-Bit Resolution  
SNR: 58.9 dBFS  
SFDR: 73 dBc  
Maximum Clock Rate: 750 Msps  
Low Swing Fullscale Input: 1.0 Vpp  
Analog Input Buffer with High Impedance Input  
Input Bandwidth (3dB): >1.2GHz  
Data Output Interface: DDR LVDS  
196-Pin BGA Package (12x12mm)  
Power Dissipation: 1050mW/ch  
Performance at fin = 230 MHz IF  
Receive Mode: 2x Decimation with Low Pass  
or High Pass Filter  
Feedback Mode: Burst Mode Output for Full  
Bandwidth DPD Feedback  
APPLICATIONS  
Telecommunications Receiver  
Power Amplifier Linearization  
SNR: 60.7 dBFS  
SFDR: 78 dBc  
Number of  
Device Part No.  
Speed Grade  
Channels  
ADS54T02  
ADS54T01  
ADS54T04  
2
1
2
750 Msps  
750 Msps  
500 Msps  
DESCRIPTION  
The ADS54T02 is a high linearity dual channel 12-bit, 750 MSPS analog-to-digital converter (ADC) easing front  
end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-  
chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Two output  
modes are available for the output data – it can be decimated by two or the data can be output in burst mode.  
The burst mode output is designed specifically for DPD feedback applications where high resolution output data  
is available for a short period of time. Designed for high SFDR, the ADC has low-noise performance and  
outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196pin  
BGA package and is specified over the full industrial temperature range (–40°C to 85°C).  
Digital Block  
12bit  
750Msps  
Burst Mode  
INA  
DA[11:0]  
DACLK  
2x Decimation  
Clk  
Buffer  
CLKIN  
TRIGGER  
SYNCIN  
Digital Block  
Burst Mode  
12bit  
750Msps  
INB  
DB[11:0]  
DBCLK  
2x Decimation  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2013, Texas Instruments Incorporated  

ADS54T02IZAYR 替代型号

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