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ADP3181JRQZ-RL PDF预览

ADP3181JRQZ-RL

更新时间: 2024-11-29 21:54:15
品牌 Logo 应用领域
亚德诺 - ADI 开关光电二极管控制器
页数 文件大小 规格书
24页 564K
描述
5-Bit or 6-Bit Programmable 2-,3-,4-Phase Synchronous Buck Controller

ADP3181JRQZ-RL 数据手册

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5-Bit or 6-Bit Programmable 2-,3-,4-Phase  
Synchronous Buck Controller  
ADP3181  
FEATURES  
FUNCTIONAL BLOCK DIAGRAM  
VCC  
RAMPADJ RT  
Selectable 2-, 3-, or 4-phase operation at up to 1 MHz per  
phase  
28  
14 13  
ADP3181  
14.5 mV worst-case mV differential sensing error over  
temperature  
Logic-level PWM outputs for interface to external high  
power drivers  
Active current balancing between all output phases  
Built-in power good/crowbar blanking supports on-the-fly  
VID code changes  
UVLO  
11  
19  
EN  
SHUTDOWN  
AND BIAS  
OSCILLATOR  
SET  
EN  
GND  
27  
RESET  
PWM1  
CMP  
DAC + 300mV  
RESET  
2-/3-/4-PHASE  
DRIVER LOGIC  
26 PWM2  
CMP  
CURRENT-  
BALANCING  
CIRCUIT  
CSREF  
25  
RESET  
PWM3  
CMP  
DAC – 250mV  
RESET  
24  
PWM4  
CMP  
Digitally programmable output can be switched between  
VRM 9 (5-bit) and VRD 10 (6-bit) VID codes for  
ADP3181JRU. (VRD10 (6-bit) only for ADP3181JRQ)  
10  
PWRGD  
DELAY  
CURRENT  
LIMIT  
CROWBAR  
23  
22  
21  
20  
17  
16  
SW1  
SW2  
SW3  
SW4  
Programmable short circuit protection with programmable  
latch-off delay  
15  
12  
ILIMIT  
APPLICATIONS  
Desktop PC power supplies for  
next-generation Intel processors  
EN  
CSSUM  
CSREF  
CURRENT-  
LIMITING  
CIRCUIT  
DELAY  
VRM modules  
18  
8
CSCOMP  
FB  
SOFT  
START  
COMP  
9
PRECISION  
REFERENCE  
VID  
DAC  
7
6
1
2
3
4
5
FBRTN CPUID  
VID4 VID3 VID2 VID1 VID0  
Figure 1.  
GENERAL DESCRIPTION  
The ADP3181 is a highly efficient multiphase synchronous  
buck-switching regulator controller optimized for converting  
a 12 V main supply into the core supply voltage required by  
high performance Intel processors. It uses an internal 6-bit  
DAC to read a voltage identification (VID) code directly from  
the processor, which is used to set the output voltage. The  
CPUID input selects whether the DAC codes match the  
VRM 9 or VRD 10 specifications. It uses a multimode PWM  
architecture to drive the logic-level outputs at a programmable  
switching frequency that can be optimized for VR size and  
efficiency. The phase relationship of the output signals can  
be programmed to provide 2-, 3-, or 4-phase operation,  
allowing for the construction of up to four complementary  
buck-switching stages.  
The ADP3181 also includes programmable no-load offset and  
slope functions to adjust the output voltage as a function of the  
load current so that it is always optimally positioned for a  
system transient. The ADP3181 provides accurate and reliable  
short-circuit protection, adjustable current limiting, and a  
delayed power good output that accommodates on-the-fly  
output voltage changes requested by the CPU.  
The device is specified over the commercial temperature range  
of 0°C to +85°C and is available in 28-lead QSOP (only VRD10  
option) and TSSOP packages.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
©2005 Analog Devices, Inc. All rights reserved.  

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