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ADP3120AJRZ-RL PDF预览

ADP3120AJRZ-RL

更新时间: 2024-11-29 06:36:23
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器MOSFET驱动器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
8页 128K
描述
Dual Bootstrapped, 12 V MOSFET Driver with Output Disable

ADP3120AJRZ-RL 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:SOIC
包装说明:SOP, SOP8,.25针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:5 weeks
风险等级:1.01Samacsys Confidence:3
Samacsys Status:ReleasedSamacsys PartID:224404
Samacsys Pin Count:8Samacsys Part Category:Integrated Circuit
Samacsys Package Category:Small Outline PackagesSamacsys Footprint Name:SOIC-8
Samacsys Released Date:2015-07-22 09:58:51Is Samacsys:N
高边驱动器:YES接口集成电路类型:HALF BRIDGE BASED MOSFET DRIVER
JESD-30 代码:R-PDSO-G8JESD-609代码:e3
长度:4.9 mm湿度敏感等级:1
功能数量:1端子数量:8
最高工作温度:85 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
电源:12 V认证状态:Not Qualified
座面最大高度:1.75 mm子类别:MOSFET Drivers
最大供电电压:13.2 V最小供电电压:4.6 V
标称供电电压:12 V表面贴装:YES
温度等级:OTHER端子面层:Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
断开时间:0.07 µs接通时间:0.045 µs
宽度:3.9 mmBase Number Matches:1

ADP3120AJRZ-RL 数据手册

 浏览型号ADP3120AJRZ-RL的Datasheet PDF文件第2页浏览型号ADP3120AJRZ-RL的Datasheet PDF文件第3页浏览型号ADP3120AJRZ-RL的Datasheet PDF文件第4页浏览型号ADP3120AJRZ-RL的Datasheet PDF文件第5页浏览型号ADP3120AJRZ-RL的Datasheet PDF文件第6页浏览型号ADP3120AJRZ-RL的Datasheet PDF文件第7页 
ADP3120A  
Dual Bootstrapped, 12 V  
MOSFET Driver with Output  
Disable  
The ADP3120A is a single Phase 12 V MOSFET gate drivers  
optimized to drive the gates of both highside and lowside power  
MOSFETs in a synchronous buck converter. The highside and  
lowside driver is capable of driving a 3000 pF load with a 45 ns  
propagation delay and a 25 ns transition time.  
With a wide operating voltage range, high or low side MOSFET  
gate drive voltage can be optimized for the best efficiency. Internal  
adaptive nonoverlap circuitry further reduces switching losses by  
preventing simultaneous conduction of both MOSFETs.  
http://onsemi.com  
MARKING  
DIAGRAMS  
8
3120A  
ALYW  
G
SO8  
D SUFFIX  
CASE 751  
8
1
1
The floating top driver design can accommodate VBST voltages as  
high as 35 V, with transient voltages as high as 40 V. Both gate outputs  
can be driven low by applying a low logic level to the Output Disable  
(OD) pin. An Undervoltage Lockout function ensures that both driver  
outputs are low when the supply voltage is low, and a Thermal  
Shutdown function provides the IC with overtemperature protection.  
1
8
DFN8  
MN SUFFIX  
CASE 506BJ  
L3C  
ALYWG  
G
1
A
L
Y
= Assembly Location  
= Wafer Lot  
Features  
= Year  
W = Work Week  
AllInOne Synchronous Buck Driver  
Bootstrapped HighSide Drive  
G
= PbFree Package  
One PWM Signal Generates Both Drives  
Anticross Conduction Protection Circuitry  
OD for Disabling the Driver Outputs Meets CPU VR Requirement  
when Used with Patented FlexModet Controller  
These are PbFree Devices  
PIN CONNECTIONS  
1
8
BST  
IN  
DRVH  
SWN  
OD  
PGND  
DRVL  
V
CC  
Applications  
1
8
Multiphase Desktop CPU Supplies  
SingleSupply Synchronous Buck Converters  
BST  
IN  
DRVH  
SWN  
OD  
PGND  
V
CC  
DRVL  
(Top View)  
ORDERING INFORMATION  
Device  
Package  
Shipping  
98 Units / Rail  
ADP3120AJRZ  
SO8  
(PbFree)  
ADP3120AJRZRL  
SO8  
(PbFree)  
2500 Tape & Reel  
5000 Tape & Reel  
ADP3120AJCPZRL DFN8  
(PbFree)  
†For information on tape and reel specifications,  
including part orientation and tape sizes, please  
refer to our Tape and Reel Packaging Specification  
Brochure, BRD8011/D.  
© Semiconductor Components Industries, LLC, 2008  
1
Publication Order Number:  
August, 2008 Rev. 3  
ADP3120A/D  

ADP3120AJRZ-RL 替代型号

型号 品牌 替代类型 描述 数据表
ADP3120AJRZ ONSEMI

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