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UCC27322TDGKREP PDF预览

UCC27322TDGKREP

更新时间: 2024-09-17 13:01:47
品牌 Logo 应用领域
德州仪器 - TI 驱动器
页数 文件大小 规格书
28页 869K
描述
Enhanced Product 9-A/9-A single-channel gate driver driver with split outputs and enable 8-VSSOP -40 to 105

UCC27322TDGKREP 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:MSOP
包装说明:TSSOP, TSSOP8,.19针数:8
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:6 weeks
风险等级:1.62接口集成电路类型:HALF BRIDGE BASED MOSFET DRIVER
JESD-30 代码:R-PDSO-G8JESD-609代码:e4
长度:3 mm湿度敏感等级:1
端子数量:8最高工作温度:105 °C
最低工作温度:-40 °C最大输出电流:9 A
标称输出峰值电流:9 A封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP8,.19
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:4.5/15 V
认证状态:Not Qualified座面最大高度:1.07 mm
子类别:MOSFET Drivers表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3 mm
Base Number Matches:1

UCC27322TDGKREP 数据手册

 浏览型号UCC27322TDGKREP的Datasheet PDF文件第2页浏览型号UCC27322TDGKREP的Datasheet PDF文件第3页浏览型号UCC27322TDGKREP的Datasheet PDF文件第4页浏览型号UCC27322TDGKREP的Datasheet PDF文件第5页浏览型号UCC27322TDGKREP的Datasheet PDF文件第6页浏览型号UCC27322TDGKREP的Datasheet PDF文件第7页 
ꢀꢁꢁ ꢂ ꢃꢄ ꢂ ꢅ ꢆ ꢀꢁ ꢁꢂ ꢃꢄ ꢂꢂ  
ꢀꢁꢁ ꢄ ꢃꢄ ꢂ ꢅ ꢆ ꢀꢁ ꢁꢄ ꢃꢄ ꢂꢂ  
SLUS504D − SEPTEMBER 2002 − REVISED SEPTEMBER 2007  
FEATURES  
APPLICATIONS  
D
D
D
D
D
D
Industry-Standard Pin-Out With Addition of  
Enable Funtion  
D
D
D
D
D
D
Switch Mode Power Supplies  
DC/DC Converters  
High-Peak Current Drive Capability of 9 A at  
the Miller Plateau Region Using TrueDrive  
Motor Controllers  
Class-D Switching Amplifiers  
Line Drivers  
Efficient Constant Current Sourcing Using a  
Unique BiPolar & CMOS Output Stage  
Pulse Transformer Driver  
TTL/CMOS Compatible Inputs Independent  
of Supply Voltage  
DESCRIPTION  
20-ns Typical Rise and Fall Times with 10-nF  
Load  
The UCC37321/2 family of high-speed drivers  
deliver 9 A of peak drive current in an industry  
standard pinout. These drivers can drive the  
largest of MOSFETs for systems requiring  
extreme Miller current due to high dV/dt  
transitions. This eliminates additional external  
circuits and can replace multiple components to  
reduce space, design complexity and assembly  
cost. Two standard logic options are offered,  
Typical Propagation Delay Times of 25 ns  
With Input Falling and 35 ns with Input  
Rising  
D
D
4-V to 15-V Supply Voltage  
Available in Thermally Enhanced MSOP  
TM  
PowerPAD  
Package With 4.7°C/W θjc  
D
Rated From –40°C to 105°C  
Pb-Free Finish (NiPdAu) on SOIC-8 and  
PDIP-8 Packages  
D
inverting  
(UCC37321)  
and  
noninverting  
(UCC37322).  
INPUT/OUTPUT TABLE  
VDD  
1
8
VDD  
ENBL  
IN  
OUT  
INVERTING  
0
0
0
1
0
0
INVERTING  
UCC37321  
7
6
OUT  
OUT  
1
1
0
0
1
1
0
1
0
1
0
1
1
0
0
0
0
1
VDD  
NON−  
INVERTING  
IN  
2
NON−  
INVERTING  
UCC37322  
R
ENBL  
100 k  
ENBL  
AGND  
3
4
5
PGND  
UDG−01112  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PowerPADt is trademarks of Texas Instruments Incorporated.  
ꢘꢧ  
Copyright 2004, Texas Instruments Incorporated  
ꢣ ꢧ ꢤ ꢣꢜ ꢝꢱ ꢟꢞ ꢢ ꢪꢪ ꢨꢢ ꢠ ꢢ ꢡ ꢧ ꢣ ꢧ ꢠ ꢤ ꢬ  
1
www.ti.com  

UCC27322TDGKREP 替代型号

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