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ADP3110KRZ PDF预览

ADP3110KRZ

更新时间: 2024-11-05 06:36:23
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器
页数 文件大小 规格书
11页 243K
描述
Dual Bootstrapped, 12 V MOSFET Driver with Output Disable

ADP3110KRZ 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:ROHS COMPLIANT, MS-012AA, SOIC-8
针数:8Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:5.57高边驱动器:YES
接口集成电路类型:HALF BRIDGE BASED MOSFET DRIVERJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
湿度敏感等级:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP8,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:12 V
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:MOSFET Drivers最大供电电压:13.2 V
最小供电电压:4.15 V标称供电电压:12 V
表面贴装:YES温度等级:OTHER
端子面层:Tin (Sn)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:3.9 mm
Base Number Matches:1

ADP3110KRZ 数据手册

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Dual Bootstrapped, 12 V MOSFET  
Driver with Output Disable  
ADP3110  
FEATURES  
GENERAL DESCRIPTION  
All-in-one synchronous buck driver  
Bootstrapped high-side drive  
The ADP3110 is a dual, high voltage MOSFET driver optimized  
for driving two N-channel MOSFETs, which are the two  
switches in a nonisolated synchronous buck power converter.  
Each of the drivers is capable of driving a 3000 pF load with a  
25 ns propagation delay and a 30 ns transition time. One of the  
drivers can be bootstrapped and is designed to handle the high  
voltage slew rate associated with floating high-side gate drivers.  
The ADP3110 includes overlapping drive protection to prevent  
shoot-through current in the external MOSFETs.  
One PWM signal generates both drives  
Anticross-conduction protection circuitry  
Output disable control turns off both MOSFETs to float  
output per Intel® VRM 10 specification  
APPLICATIONS  
Multiphase desktop CPU supplies  
Single-supply synchronous buck converters  
The OD pin shuts off both the high-side and the low-side  
MOSFETs to prevent rapid output capacitor discharge during  
system shutdown.  
The ADP3110 is specified over the commercial temperature  
range of 0°C to 85°C and is available in an 8-lead SOIC_N  
package.  
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM  
12V  
D1  
VCC  
4
BST  
ADP3110  
1
8
C
BST2  
C
BST1  
2
R
G
IN  
DRVH  
Q1  
DELAY  
R
BST  
TO  
INDUCTOR  
SW  
7
CMP  
VCC  
6
CMP  
DRVL  
PGND  
1V  
CONTROL  
LOGIC  
5
6
Q2  
DELAY  
3
OD  
Figure 1.  
©2010 SCILLC. All rights reserved.  
May 2010 – Rev. 2  
Publication Order Number:  
ADP3110/D  

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