Datasheet > ADN2855ACPZ-R7

ADN2855ACPZ-R7

更新时间： 2024-02-19 15:31:25

品牌	Logo	应用领域
亚德诺 - ADI		外围集成电路
页数	文件大小	规格书
21页	433K
描述
Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps Burst Mode Clock and Data Recovery IC with Deserializerer

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技术参数
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ADN2855ACPZ-R7 技术参数

是否无铅：	含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	5A991.B.3
HTS代码：	8542.39.00.01	风险等级：	5.07
Is Samacsys：	N	JESD-30 代码：	S-XQCC-N32
JESD-609代码：	e3	长度：	5 mm
湿度敏感等级：	1	端子数量：	32
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	5 mm	uPs/uCs/外围集成电路类型：	MICROPROCESSOR CIRCUIT
Base Number Matches：	1

ADN2855ACPZ-R7 数据手册

Data Sheet

ADN2855

APPLICATIONS INFORMATION

should be placed between the IC power supply VCC and VEE,

as close as possible to the ADN2855 VCC pins.

PCB DESIGN GUIDELINES

Proper RF PCB design techniques must be used for optimal

performance.

If connections to the supply and ground are made through vias,

the use of multiple vias in parallel helps to reduce series inductance.

Refer to the schematic in Figure 17 for recommended connections.

Power Supply Connections and Ground Planes

Use of one low impedance ground plane is recommended. The

VEE pins should be soldered directly to the ground plane to

reduce series inductance. If the ground plane is an internal

plane and connections to the ground plane are made through

vias, multiple vias can be used in parallel to reduce the series

inductance. The exposed pad should be connected to the GND

plane using plugged vias so that solder does not leak through

the vias during reflow.

By using adjacent power supply and GND planes, excellent high

frequency decoupling can be realized by using close spacing

between the planes. This capacitance is given by

C_PLANE

[

pf = 0.88ε_rA/d

]

where:

ε_ris the dielectric constant of the PCB material.

A is the area of the overlap of power and GND planes (cm²).

d is the separation between planes (mm).

For FR-4, ε_r= 4.4 mm and 0.25 mm spacing, C_PLANE≈ 15 pF/cm².

Use of a 10 µF electrolytic capacitor between VCC and VEE is

recommended at the location where the 3.3 V supply enters the

PCB. When using 0.1 µF and 1 nF ceramic chip capacitors, they

VCC

0.1µF

VCC

OLT SYSTEM

CLOCK

0.47µF

0.1µF

VCC

1nF

REFCLKP,

REFCLKN

CF1

CF2

VEE VCC

0.1µF

FREQ,

LOCK

DET

LOOP

FILTER

RESET

NIN

LAOUTP PIN

LAOUTN NIN

PHASE

SHIFTER

CML INPUT

BUFFER

LOOP

FILTER

PHASE

DET

VCO

ADN2855

DATA

RETIMING

DESERIALIZER

DIVIDER

I C

4 × 2

SQUELCH

DATxP,

DATxN

CLKOUTP,

CLKOUTPN

OLT MAC

Figure 17. Typical Application Circuit

Rev. B | Page 15 of 20

1...13 14 151617 18 19...21

中文翻译

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与ADN2855ACPZ-R7相关器件

型号	品牌	获取价格	描述	数据表
ADN2855-EVALZ	ADI	获取价格	Multirate 155 Mbps/622 Mbps/1244 Mbps/1250 Mbps Burst Mode Clock and Data Recovery IC with
ADN2860	ADI	获取价格	3-Channel Digital Potentiometer with Nonvolatile Memory
ADN2860ACPZ250	ADI	获取价格	IC TRIPLE 250K DIGITAL POTENTIOMETER, INCREMENT/DECREMENT CONTROL INTERFACE, 512 POSITIONS
ADN2860ACPZ250-RL7	ADI	获取价格	3-Channel Digital Potentiometer with Nonvolatile Memory
ADN2860ACPZ25-RL7	ADI	获取价格	3-Channel Digital Potentiometer with Nonvolatile Memory
ADN2860-EVAL	ADI	获取价格	3-Channel Digital Potentiometer with Nonvolatile Memory
ADN2865	ADI	获取价格	Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC w/Loop Timed SERDES
ADN2865ACP	ADI	获取价格	Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC w/Loop Timed SERDES
ADN2865ACP-RL	ADI	获取价格	Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC w/Loop Timed SERDES
ADN2865ACP-RL7	ADI	获取价格	Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery IC w/Loop Timed SERDES

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