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ADM9240ARUZ-REEL

更新时间： 2024-02-07 02:07:28
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管
页数 文件大小 规格书
22页 280K
描述
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24, TSSOP-24, Power Management Circuit

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ADM9240ARUZ-REEL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：TSSOP
包装说明：TSSOP-24针数：24
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.15
可调阈值：NO模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：R-PDSO-G24JESD-609代码：e3
长度：7.8 mm信道数量：1
功能数量：1端子数量：24
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.1 mm最大供电电压 (Vsup)：5.75 V
最小供电电压 (Vsup)：2.85 V标称供电电压 (Vsup)：5 V
表面贴装：YES温度等级：AUTOMOTIVE
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

ADM9240ARUZ-REEL 数据手册

 浏览型号ADM9240ARUZ-REEL的Datasheet PDF文件第16页浏览型号ADM9240ARUZ-REEL的Datasheet PDF文件第17页浏览型号ADM9240ARUZ-REEL的Datasheet PDF文件第18页浏览型号ADM9240ARUZ-REEL的Datasheet PDF文件第19页浏览型号ADM9240ARUZ-REEL的Datasheet PDF文件第21页浏览型号ADM9240ARUZ-REEL的Datasheet PDF文件第22页 
ADM9240  
Table X. Register 43h, INT Interrupt Mask Register 1 (P ower-O n D efault = 00h)  
Bit  
Nam e  
R/W  
D escription  
0
1
2
3
4
5
6
7
+2.5 V  
+VCCP1  
+3.3 V  
+5 V  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
A “1” disables the corresponding interrupt status bit for INT interrupt.  
A “1” disables the corresponding interrupt status bit for INT interrupt.  
A “1” disables the corresponding interrupt status bit for INT interrupt.  
A “1” disables the corresponding interrupt status bit for INT interrupt.  
A “1” disables the corresponding interrupt status bit for INT interrupt.  
Power-On Default = 0.  
T emp  
Reserved  
FAN1  
FAN2  
A “1” disables the corresponding interrupt status bit for INT interrupt.  
A “1” disables the corresponding interrupt status bit for INT interrupt.  
Table XI. Register 44h, INT Mask Register 2 (P ower-O n D efault = 00h)  
Bit  
Nam e  
R/W  
D escription  
0
1
2
3
4
5
6
7
+12 V  
VCCP2  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
Read/Write  
A “1” disables the corresponding interrupt status bit for INT interrupt.  
A “1” disables the corresponding interrupt status bit for INT interrupt.  
Power-up default set to Low.  
Power-up default set to Low.  
A “1” disables the corresponding interrupt status bit for INT interrupt.  
Undefined.  
Reserved  
Reserved  
CI  
Reserved  
Reserved  
RESET Enable  
Undefined.  
A “1” enables the RESET function in the configuration register.  
Table XII. Register 45h, Reserved Com patibility (P ower-O n D efault = 00h)  
Bit  
Nam e  
R/W  
D escription  
0–7  
Reserved  
Read/Write  
Reserved for Compatibility.  
Table XIII. Register 46h, Chassis Intrusion Clear (P ower-O n D efault = 00h)  
Bit  
Nam e  
R/W  
D escription  
0–6  
7
Reserved  
Chassis Int. Clear  
Read/Write  
Read/Write  
Undefined (Power On Default = 00h)  
A “1” outputs a minimum 20 ms active low pulse on the chassis intrusion  
pin. T he register bit clears itself after the pulse has been output.  
Table XIV. Register 47h, VID 0–3/Fan D ivisor Register (P ower-O n D efault 0101(VID 3–VID 0))  
Bit  
Nam e  
R/W  
D escription  
0–3  
VID  
Read  
T he VID[3:0] inputs from processor core power supplies to indicate the  
operating voltage (e.g., 1.3 V to 3.5 V).  
Sets Counter Prescaler for FAN1 Speed Measurement  
<5:4> = 00 – Divide by 1  
4–5  
FAN1 Divisor  
Read/Write  
<5:4> = 01 – Divide by 2  
<5:4> = 10 – Divide by 4  
<5:4> = 11 – Divide by 8  
6–7  
FAN2 Divisor  
Read/Write  
Sets Counter Prescaler for FAN2 Speed Measurement  
<7:6> = 00 – Divide by 1  
<7:6> = 01 – Divide by 2  
<7:6> = 10 – Divide by 4  
<7:6> = 11 – Divide by 8  
–20–  
REV. 0  
1...171819202122

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