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ADM9240ARUZ-REEL PDF预览

ADM9240ARUZ-REEL

更新时间： 2024-02-22 01:27:59
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管
页数 文件大小 规格书
22页 280K
描述
IC 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO24, TSSOP-24, Power Management Circuit

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ADM9240ARUZ-REEL 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Transferred零件包装代码：TSSOP
包装说明：TSSOP-24针数：24
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.15
可调阈值：NO模拟集成电路 - 其他类型：POWER SUPPLY SUPPORT CIRCUIT
JESD-30 代码：R-PDSO-G24JESD-609代码：e3
长度：7.8 mm信道数量：1
功能数量：1端子数量：24
最高工作温度：125 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度（摄氏度）：260认证状态：Not Qualified
座面最大高度：1.1 mm最大供电电压 (Vsup)：5.75 V
最小供电电压 (Vsup)：2.85 V标称供电电压 (Vsup)：5 V
表面贴装：YES温度等级：AUTOMOTIVE
端子面层：Matte Tin (Sn)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：4.4 mm
Base Number Matches：1

ADM9240ARUZ-REEL 数据手册

 浏览型号ADM9240ARUZ-REEL的Datasheet PDF文件第16页浏览型号ADM9240ARUZ-REEL的Datasheet PDF文件第17页浏览型号ADM9240ARUZ-REEL的Datasheet PDF文件第18页浏览型号ADM9240ARUZ-REEL的Datasheet PDF文件第20页浏览型号ADM9240ARUZ-REEL的Datasheet PDF文件第21页浏览型号ADM9240ARUZ-REEL的Datasheet PDF文件第22页 
ADM9240  
Table VII. Register 40h, Configuration Register (P ower-O n D efault = 08h)  
R/W D escription  
Bit  
Nam e  
0
ST ART  
R/W  
Logic 1 enables startup of ADM9240, Logic 0 places it in standby mode. Caution: the out-  
puts of the Interrupt pins will not be cleared if the user writes a zero to this location after an  
interrupt has occurred (see “INT_Clear” bit). At startup, limit checking functions and scan-  
ning begins. Note, all high and low limits should be set into the ADM9240 prior to turning  
on this bit. (Power-Up Default = 0.)  
1
2
3
INT_Enable  
Reserved  
R/W  
R/W  
Logic 1 enables the INT output. 1 = Enabled 0 = Disabled (Power-Up Default = 0).  
Default = 0.  
INT_Clear  
During Interrupt Service Routine (ISR) this bit is asserted Logic 1 to clear INT output  
without affecting the contents of the Interrupt Status Register. T he device will stop monitor-  
ing. It will resume upon clearing of this bit. (Power-Up Default = 1.)  
4
RESET  
R/W  
Creates a RESET (Active Low) signal for 20 ms minimum (Power-Up Default = 0).  
T his bit is cleared once the pulse goes active.  
5
6
Reserved  
CI_Reset  
R/W  
R/W  
Default = 0.  
A “1” outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. (Power-Up  
Default = 0.) (Note: T his bit performs the same function as Bit 7 in Register 46h).  
7
Initialization  
R/W  
Logic 1 restores power-up default values to the Configuration register, Interrupt status regis-  
ters, Interrupt Mask Registers, Fan Divisor Register and the T emperature Configuration  
Register. T his bit automatically clears itself since the power-on default is zero.  
Table VIII. Register 41h, Interrupt Status Register 1 (P ower-O n D efault = 00h)  
Bit  
Nam e  
R/W  
D escription  
0
1
2
3
4
5
6
7
+2.5 V_Error  
VCCP_Error  
+3.3 V_Error  
+5 V_Error  
T emp_Error  
Reserved  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
A “1” indicates a high or low limit has been exceeded.  
A “1” indicates a high or low limit has been exceeded.  
A “1” indicates a high or low limit has been exceeded.  
A “1” indicates a high or low limit has been exceeded.  
A “1” indicates that a temperature interrupt has been set.  
Undefined.  
FAN1_Error  
FAN2_Error  
A “1” indicates that a fan count limit has been exceeded.  
A “1” indicates that a fan count limit has been exceeded.  
Table IX. Register 42h, Interupt Status Register 2 (P ower-O n D efault = 00h)  
Bit  
Nam e  
R/W  
D escription  
0
1
2
3
4
5
6
7
+12 V_Error  
VCCP2_Error  
Reserved  
Reserved  
Chassis_Error  
Reserved  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
Read Only  
A “1” indicates a high or low limit has been exceeded.  
A “1” indicates a high or low limit has been exceeded.  
Undefined.  
Undefined.  
A “1” indicates chassis intrusion has gone high.  
Undefined.  
Undefined.  
Undefined.  
Reserved  
Reserved  
Note: Any time the ST AT US Register is read out, the conditions (i.e., Register) that are read are automatically reset. In the case of the channel priority indication, if  
two or more channels were out of limits, another indication would automatically be generated if it were not handled during the ISR. In the Mask Register, the errant  
voltage interrupt may be disabled until the operator has time to clear the errant condition or set the limit higher/lower.  
REV. 0  
–19–  
1...16171819202122

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