Hot-Swap Controller and Digital Power
Monitor with PMBus Interface
Data Sheet
ADM1275
FEATURES
APPLICATIONS DIAGRAM
R
SENSE
Q
2V TO 20V
1
Controls supply voltages from 2 V to 20 V
370 ns response time to short circuit
SENSE+
SENSE–
2.95V
TO
20V
VCC
–
Resistor-programmable 5 mV to 25 mV current limit
1% accurate, 12-bit ADC for current, VIN/VOUT readback
Charge-pumped gate drive for multiple external N-channel FETs
High gate drive voltage to ensure lowest RDSON
Foldback for tighter FET SOA protection
Automatic retry or latch-off on current fault
Programmable current limit timer for SOA
Programmable, multifunction GPOs
Power-good status output
Analog UV and OV protection
ENABLE pin (ADM1275-3 only)
Peak detect registers for current and voltage
PMBus fast mode compliant interface
ADM1275-1
+
×50
CHARGE
PUMP
VCAP
UV
LDO
+
IOUT
V
CP
GATE
DRIVE/
LOGIC
1.0V
–
GATE
VOUT
OV
–
TIMEOUT
CURRENT
1.0V
+
+
–
ISET
REF
SELECT
LIMIT
TIMER
ON
1.0V
CURRENT
LIMIT
CONTROL
V
CBOS
SS
TIMER
ON
FLB
TIMER
TIMER
PWRGD
TIMEOUT
GPO1/ALERT1/CONV
GPO2/ALERT2
LATCH
SCL
LOGIC
AND
PMBus
SENSE+
VOUT
IOUT
12-BIT
ADC
SDA
ADR
16-lead QSOP and 20-lead QSOP and LFCSP
GND
APPLICATIONS
Figure 1.
Power monitoring and control/power budgeting
Central office equipment
Telecommunication and data communication equipment
PCs/servers
GENERAL DESCRIPTION
The ADM1275 is a hot-swap controller that allows a circuit board
to be removed from or inserted into a live backplane. It also features
current and voltage readback via an integrated 12-bit analog-to-
digital converter (ADC), accessed using a PMBus™ interface.
In case of a short-circuit event, a fast internal overcurrent detec-
tor responds within 370 ns and signals the gate to shut down. A
1500 mA pull-down device ensures a fast FET response. The
ADM1275 features overvoltage and undervoltage protection,
programmed using external resistor dividers on the UV and OV
pins. A PWRGD signal can be used to detect when the output
supply is valid, using the FLB pin to monitor the output. GPO
pins can be configured as various output signals that can be
asserted when a programmed current or voltage level is reached.
The load current is measured using an internal current sense
amplifier that measures the voltage across a sense resistor in
the power path via the SENSE+ and SENSE− pins. A default
limit of 20 mV is set, but this limit can be adjusted, if required,
using a resistor divider network from the internal reference
voltage to the ISET pin.
The 12-bit ADC can measure the current in the sense resistor,
as well as the supply voltage on the SENSE+ pin or the output
voltage. A PMBus interface allows a controller to read current
and voltage data from the ADC. Measurements can be initiated
by a PMBus command. Alternatively, the ADC can run continu-
ously, and the user can read the latest conversion data whenever
required. Up to four unique PMBus addresses can be selected,
depending on the way that the ADR pin is connected.
The ADM1275 limits the current through the sense resistor by
controlling the gate voltage of an external N-channel FET in the
power path, via the GATE pin. The sense voltage—and, therefore,
the load current—is maintained below the preset maximum. The
ADM1275 protects the external FET by limiting the time that the
FET remains on while the current is at its maximum value. This
current limit time is set by the choice of capacitor connected to
the TIMER pin. In addition, a foldback resistor network can be
used to actively lower the current limit as the voltage across the
FET is increased. This helps to maintain constant power in the
FET and allows the safe operating area (SOA) to be adhered to
in an effective manner.
The ADM1275-1 and ADM1275-3 are available in a 20-lead QSOP
LATCH
and 20-lead LFCSP and have a
pin that can be configured
for automatic retry or latch-off when an overcurrent fault occurs.
The ADM1275-2 is available in a 16-lead QSOP with latch-off
mode only.
Rev. D
Document Feedback
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Tel: 781.329.4700 ©2010–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
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