Cascadable Super Sequencer with Margin
Control and Fault Recording
Data Sheet
ADM1266
FEATURES
GENERAL DESCRIPTION
Complete supervisory and sequencing solution for up to
17 supplies
The ADM1266 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in systems with up to 17 supplies.
For systems with more supplies (up to 257), the operation of up
to 16 ADM1266 devices can be synchronized through a proprie-
tary 2-wire interface (interdevice bus).
Expandable to 257 supplies with additional ADM1266 ICs
connected to the 2-wire interdevice bus
Fully programmable sequencing engine
17 supply fault detectors enable real time supervision of
supplies
The sequencing engine (SE) monitors the supply fault detectors
(SFDs), programmable driver input/outputs (PDIOs), general-
purpose inputs/outputs (GPIOs), and timers, and controls the
PDIOs and GPIOs to sequence the supplies up and down as
required. The logical core of the device is an ARM® Cortex-M3
microcontroller. The firmware is supplied by Analog Devices,
Inc., and all configuration is performed through an intuitive
graphic user interface (GUI).
0.4 V to 15 V on VH1 to VH4 (VHx)
0.4 V to 5 V on VP1 to VP13 (VPx)
Device powered by the higher of VH1 and VH2 inputs for
improved operating redundancy
12-bit ADC for readback of all supervised voltages
Black box nonvolatile fault recording
16 PDIOs
9 GPIOs
Additionally, the ADM1266 integrates an analog-to-digital
converter (ADC) and voltage output digital-to-analog converters
(DACs) that can be used to adjust either the feedback node or
reference of a dc-to-dc converter to implement a closed-loop,
autonomous, margining system.
9 voltage output 8-bit DACs allow voltage margining
adjustment via dc-to-dc converter trim/feedback node
Main and backup memory
Industry standard PMBus interface compliant
Available in a 9 mm × 9 mm, 64-lead package
A block of nonvolatile EEPROM is available to record voltage,
time, and fault information when instructed to by the sequencing
engine configuration.
APPLICATIONS
Communications infrastructure
Industrial test and measurement
FUNCTIONAL BLOCK DIAGRAM
PDIO1
PROGRAMMABLE
DRIVE
+
GLITCH
FILTER
VH1
OV
DAC
–
OUTPUTS/INPUTS
PDIO16
PROGRAMMABLE
SEQUENCING
ENGINE
VH4
VP1
UV
DAC
+
–
GPIO1
GPIO9
GLITCH
FILTER
GPIOs
LOGIC BLOCK
MARGINING
ID_SDA
ID_SCL
VP13
INTERDEVICE
BUS
DAC1
DAC9
DAC
DAC
CONTROL
DAC
SCL
SDA
EEPROM AND SRAM
PMBus
INTERFACE
12-BIT
SAR ADC
Figure 1.
Rev. A
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