Datasheet > ADM1027ARQZ-RL71

ADM1027ARQZ-RL71

更新时间： 2022-03-04 06:41:03

品牌	Logo	应用领域
安森美 - ONSEMI		监视器控制器
页数	文件大小	规格书
56页	1815K
描述
dBCOOLâ¢ Remote Thermal Controller and Voltage Monitor

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数据手册

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ADM1027ARQZ-RL71 数据手册

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ADM1027

Table XXIV. XOR Tree Test Enable

R/W

Description

XOR Tree Test Enable Register

Power-On Default

0x6F

Read/Write

0x00

<0>

XEN

If the XEN bit is set to 1, the device enters the XOR tree test mode. Clearing the bit

removes the device from the XOR tree test mode.

<7:1>

Reserved

Unused. Do not write to these bits.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register

will have no effect.

Table XXV. Remote 1 Temperature Offset

R/W

Description

Power-On Default

0x70

Read/Write

Remote 1 Temperature Offset

0x00

<7:0>

Read/Write

Allows a twos complement offset value to be automatically added to or subtracted from

the Remote 1 temperature reading. This is to compensate for any inherent system offsets

such as PCB trace resistance. LSB value = 1^oC.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register

will have no effect.

Table XXVI. Local Temperature Offset

R/W

Description

Power-On Default

0x71

Read/Write

Local Temperature Offset

0x00

<7:0>

Read/Write

Allows a twos complement offset value to be automatically added to or subtracted from

the local temperature reading. LSB value = 1^oC.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register

will have no effect.

Table XXVII. Remote 2 Temperature Offset

R/W

Description

Power-On Default

0x72

Read/Write

Remote 2 Temperature Offset

0x00

<7:0>

Read/Write

Allows a twos complement offset value to be automatically added to or subtracted from

the Remote 2 temperature reading. This is to compensate for any inherent system off-

sets such as PCB trace resistance. LSB value = 1^oC.

This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any further attempts to write to this register

will have no effect.

Rev. 3 | Page 51 of 56 | www.onsemi.com

REV. A

–51–

1...48 49 505152 53 54...56

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