Data Sheet
ADG1206L/ADG1207L
Low Capacitance, 16-Channel and 8-Channel iCMOS Multiplexers with 1.2 V and
1.8 V JEDEC Logic Compliance
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
► <1 pC charge injection over full signal range
► 1.5 pF off capacitance
► 120 Ω on resistance
► Fully specified at ±15 V/+12 V
► VL supply for low logic-level compatibility
► 1.8 V JEDEC standard compliant (JESD8-7A)
► 1.2 V JEDEC standard compliant (JESD8-12A.01)
► Rail-to-rail operation
► Break-before-make switching action
► 32-lead, 5 mm × 5 mm LFCSP
APPLICATIONS
Figure 1. ADG1206L Functional Block Diagram
► Audio and video routing
► Automatic test equipment
► Data acquisition systems
► Battery-powered systems
► Sample-and-hold systems
► Communication systems
► FPGA and microcontroller systems
GENERAL DESCRIPTION
®
The ADG1206L/ADG1207L are monolithic iCMOS analog multi-
plexers comprising sixteen single channels and eight differential
channels, respectively. The ADG1206L switches one of sixteen in-
puts to a common output, as determined by the 4‑bit binary address
lines A0, A1, A2, and A3. The ADG1207L switches one of eight
differential inputs to a common differential output, as determined by
the 3-bit binary address lines A0, A1, and A2. An EN input on both
devices is used to enable or disable the device. When disabled, all
channels are switched off. When on, each channel conducts equally
well in both directions and has an input signal range that extends to
the supplies.
Figure 2. ADG1207L Functional Block Diagram
PRODUCT HIGHLIGHTS
1. Ultralow capacitance.
2. Guaranteed switch off when digital inputs are floating.
An external low voltage (VL) supply provides flexibility for lower
logic control. The ADG1206L/ADG1207L are both 1.2 V and 1.8 V
JEDEC standard compliant.
Rev. 0
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