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ADF7012BRU-U1

更新时间： 2024-02-07 05:21:34
品牌 Logo 应用领域
亚德诺 - ADI 光电二极管
页数 文件大小 规格书
28页 630K
描述
IC,RF MODULATOR,CMOS,TSSOP,24PIN,PLASTIC

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ADF7012BRU-U1 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：TSSOP, TSSOP24,.25Reach Compliance Code：not_compliant
风险等级：5.92JESD-30 代码：R-PDSO-G24
JESD-609代码：e0端子数量：24
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP24,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH电源：2.5/3.3 V
认证状态：Not Qualified子类别：Other Telecom ICs
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn85Pb15)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUALBase Number Matches：1

ADF7012BRU-U1 数据手册

 浏览型号ADF7012BRU-U1的Datasheet PDF文件第19页浏览型号ADF7012BRU-U1的Datasheet PDF文件第20页浏览型号ADF7012BRU-U1的Datasheet PDF文件第21页浏览型号ADF7012BRU-U1的Datasheet PDF文件第23页浏览型号ADF7012BRU-U1的Datasheet PDF文件第24页浏览型号ADF7012BRU-U1的Datasheet PDF文件第25页 
ADF7012  
868 MHZ OPERATION  
The recommendations here are guidelines only. The design  
should be subject to internal testing prior to ETSI site testing.  
Matching components need to be adjusted for board layout.  
The modulation steps available are in 4.9152 MHz/214 :  
Modulation steps = 300 Hz  
Modulation number = 19.2 kHz/300 Hz = 64.  
Bias Current  
The ETSI standard EN 300-220 governs operation in the  
868 MHz to 870MHz band. The band is broken down into  
several subbands each having a different duty cycle and output  
power requirement. Narrowband operation is possible in the  
50kHz channels, but both the output power and data rate are  
limited by the −36 dBm adjacent channel power specification.  
There are many different applications in this band, including  
remote controls for security, sensor interrogation, metering  
and home control.  
Because low current is desired, a 2.5 mA VCO bias can be used.  
Additional bias current reduces any spurious, but increases  
current consumption. A 2.5 mA bias current gives the best  
spurious vs. phase noise trade-off.  
The PA bias should be set to 7.5 mA to achieve 12 dBm.  
Loop Filter Bandwidth  
The loop filter is designed with ADIsimPLL Version 2.5. The  
loop bandwidth design requires that the channel power be  
< −36 dBm at 250 kHz from the center. A loop bandwidth of  
close to <60 kHz is required to bring the phase noise at the edge  
of the band sufficiently low to meet the ACP specification. This  
represents a compromise between the data rate requirement and  
the phase noise requirement.  
Design Criteria  
868.95 MHz center frequency (band 868.7MHz − 869.2 MHz)  
FSK modulation  
12 dBm output power  
300 m range  
Meets ETSI 300-220  
38.4 kbps data rate  
Design of Harmonic Filter  
The main requirement of the harmonic filter should ensure that  
the second and third harmonic levels are < −30 dBm. A fifth-  
order Chebyshev filter is recommended to achieve this, and a  
suggested starting point is given next. The Pi format is chosen  
to minimize the more expensive inductors.  
The design challenge is to enable the part to operate in this  
particular subband and meet the ACP requirement 250 kHz  
away from the center.  
The center frequency is 868.95 MHz. It is possible to operate the  
VCO at this frequency. Figure 31 shows the inductor value vs.  
center frequency. The inductor chosen is 1.9 nH. Coilcraft  
inductors such as 0402-CS-1N9XJBU are recommended.  
Component Values—Crystal: 4.9152 MHz  
Loop Filter  
Icp  
LBW  
C1  
1.44 mA  
60 kHz  
1.5 nF  
22 nF  
Crystal and PFD  
The phase noise requirement is such to ensure the power at  
the edge of the band is < −36 dBm. This requires close to  
−100 dBc/Hz phase noise at the edge of the band.  
C2  
C3  
560 pF  
R1  
390 V  
The PFD is chosen so as to minimize spurious levels (beat note  
and reference), and to ensure a quick crystal power-up time. A  
PFD of < 6 MHz places the largest PFD spur at a frequency of  
greater than 862 MHz, and so reduces the requirement on the  
spur level to −36 dBm instead of −54 dBm.  
R2  
910 V  
Matching  
L1  
L2  
C14  
27 nH  
6.2 nH  
470 pF  
Open  
PFD = 4.9152 MHz − Power Up-Time 1.6 ms. Figure 10 shows a  
typical power-on time for a 4MHz crystal.  
C15  
Harmonic Filter  
L4  
L5  
CF1  
CF2  
CF3  
N-Divider  
8.2 nH  
8.2 nH  
4.7 pF  
6.8 pF  
4.7 pF  
The N divider is determined as being:  
Nint = 176  
Nfrac = (3229)/4096  
VCO divide-by-2 is not enabled.  
Deviation  
The deviation is set to 19.2 kHz so as to accommodate a  
simple receiver architecture and also ensure that the  
modulation spectrum is narrow enough to meet the adjacent  
channel power (ACP) requirements.  
Rev. 0 | Page 22 of 28  
 
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